A method for producing a joined structure according to the present invention includes: a reflow step of heating a first member and a solder material while keeping them in contact with each other in a reflow chamber to melt a solder alloy constituting the solder material, the reflow step including: a first reflow step of melting the solder alloy with an atmosphere in the reflow chamber reduced to a first pressure P.sub.1 lower than the atmospheric pressure; and a second reflow step of, after the first reflow step, melting the solder alloy with the atmosphere in the reflow chamber reduced to a second pressure P.sub.2 lower than the first pressure P.sub.1.

A method for producing a joined structure according to the present invention includes: a reflow step of heating a first member and a solder material while keeping them in contact with each other in a reflow chamber to melt a solder alloy constituting the solder material, the reflow step including: a first reflow step of melting the solder alloy with an atmosphere in the reflow chamber reduced to a first pressure P.sub.1 lower than the atmospheric pressure; and a second reflow step of, after the first reflow step, melting the solder alloy with the atmosphere in the reflow chamber reduced to a second pressure P.sub.2 lower than the first pressure P.sub.1.

The present disclosure is directed to a compact vertical oven for reflow of solder bumps for backend processes in semiconductor wafer assembly and packaging. This disclosure describes a vertical oven which uses a plurality of wafers (e.g., an example value is 50-100 wafers) in a batch with controlled injection of the reducing agent (e.g. formic acid), resulting in a process largely free of contamination. This disclosure describes controlled formic acid flow through a vertical system using laminar flow technology in a sub-atmospheric pressure environment, which is not currently available in the industry. The efficacy of the process depends on effective formic acid vapor delivery, integrated temperature control during heating and cooling, and careful design of the vapor flow path with exhaust. Zone-dependent reaction dynamics managed by vapor delivery process, two-steps temperature ramp control, and controlled cooling process and formic acid content ensures the effective reaction without any flux.

A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.

The present invention provides a highly reliable solder joint, the solder joint including a solder joint layer having a melted solder material containing Sn as a main component and further containing Ag and/or Sb and/or Cu; and a joined body including a Ni—P—Cu plating layer on a surface in contact with the solder joint layer, wherein the Ni—P—Cu plating layer contains Ni as a main component and contains 0.5% by mass or greater and 8% by mass or less of Cu and 3% by mass or greater and 10% by mass or less of P, the Ni—P—Cu plating layer has a microcrystalline layer at an interface with the solder joint layer, and the microcrystalline layer includes a phase containing microcrystals of a NiCuP ternary alloy, a phase containing microcrystals of (Ni,Cu).sub.3P, and a phase containing microcrystals of Ni.sub.3P.

A lead-free solder alloy includes 2.0% by mass or more and 4.0% by mass or less of Ag, 0.3% by mass or more and 0.7% by mass or less of Cu, 1.2% by mass or more and 2.0% by mass or less of Bi, 0.5% by mass or more and 2.1% by mass or less of In, 3.0% by mass or more and 4.0% by mass or less of Sb, 0.001% by mass or more and 0.05% by mass or less of Ni, 0.001% by mass or more and 0.01% by mass or less of Co, and the balance being Sn.

Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

A semiconductor package includes a package substrate and a semiconductor chip mounted on the package substrate. The package substrate includes a signal bump land and an anchoring bump land, and the semiconductor chip includes a signal bump and an anchoring bump. The signal bump is bonded to the signal bump land, the anchoring bump is disposed to be adjacent to the anchoring bump land, and a bottom surface of the anchoring bump is located at a level which is lower than a top surface of the anchoring bump land with respect to a surface of the package substrate.

A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.