A semiconductor assembly packaging method, a semiconductor assembly and an electronic device are provided. The method comprises providing an interconnect board and at least one semiconductor device; aligning and attaching the at least one semiconductor device to the interconnect board by forming a plurality of alignment solder joints; applying pressure to the at least one semiconductor device and/or the interconnect board while the alignment solder joints are in a molten or partially molten state, whereby first connection terminals on the interconnect board are joined with and bonded to corresponding second connection terminals on the at least one semiconductor device. Using the packaging method, the semiconductor device and the interconnect board can be aligned accurately using relatively simple and low cost processes and equipment. The method can also be used to align and bond at least one semiconductor device to another semiconductor device.

A semiconductor assembly packaging method, a semiconductor assembly and an electronic device are provided. The method comprises providing an interconnect board and at least one semiconductor device; aligning and attaching the at least one semiconductor device to the interconnect board by forming a plurality of alignment solder joints; applying pressure to the at least one semiconductor device and/or the interconnect board while the alignment solder joints are in a molten or partially molten state, whereby first connection terminals on the interconnect board are joined with and bonded to corresponding second connection terminals on the at least one semiconductor device. Using the packaging method, the semiconductor device and the interconnect board can be aligned accurately using relatively simple and low cost processes and equipment. The method can also be used to align and bond at least one semiconductor device to another semiconductor device.

A method of using an oven includes supporting a substrate on a rotatable spindle in a processing chamber of the oven and rotating the substrate. The method may also include raising the spindle with the substrate to a heating zone and activating a lamp assembly to heat a top surface of the substrate. The substrate may then be lowered to a dosing zone and a chemical vapor directed into the processing chamber above the substrate. The substrate may then be further heated using the lamp assembly and cooled.

An apparatus for forming a package structure is provided. The apparatus includes a processing chamber for bonding a first package component and a second package component. The apparatus also includes a bonding head disposed in the processing chamber. The bonding head includes a plurality of vacuum tubes communicating with a plurality of vacuum devices. The apparatus further includes a nozzle connected to the bonding head and configured to hold the second package component. The nozzle includes a plurality of first holes that overlap the vacuum tubes. The nozzle also includes a plurality of second holes offset from the first holes, wherein the second holes overlap at least two edges of the second package component. In addition, the apparatus includes a chuck table disposed in the processing chamber, and the chuck table is configured to hold and heat the first package component.

A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.

According to one embodiment, a method of manufacturing a semiconductor device includes forming a metal bump on a first surface side of a semiconductor chip, positioning the semiconductor chip so the metal bump contacts a pad of an interconnection substrate, and applying a first light from a second surface side of the semiconductor chip and melting the metal bump with the first light. After the melting, the melted metal bump is allowed to resolidify by stopping or reducing the application of the first light. The semiconductor chip is then pressed toward the interconnection substrate. A second light is then applied from the second surface side of the semiconductor chip while the semiconductor chip is being pressed toward the interconnection substrate to melt the metal bump. After the melting, the melted metal bump is allowed to resolidify by the stopping or reducing of the application of the second light.

A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.

The present disclosure relates to a method for manufacturing a semiconductor package including vacuum-laminating a non-conductive film on a substrate on which a plurality of through silicon vias are provided and bump electrodes are formed, and then performing UV irradiation, wherein an increase in melt viscosity before and after UV irradiation can be adjusted to 30% or less, whereby a bonding can be performed without voids during thermo-compression bonding, and resin-insertion phenomenon between solders can be prevented, fillets can be minimized and reliability can be improved.

The present disclosure relates to a method for manufacturing a semiconductor package including vacuum-laminating a non-conductive film on a substrate on which a plurality of through silicon vias are provided and bump electrodes are formed, and then performing UV irradiation, wherein an increase in melt viscosity before and after UV irradiation can be adjusted to 30% or less, whereby a bonding can be performed without voids during thermo-compression bonding, and resin-insertion phenomenon between solders can be prevented, fillets can be minimized and reliability can be improved.

A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.