A thermosetting composition for use as an underfill material contains: a mono- or bifunctional acrylic compound; a thermo-radical polymerization initiator; silica; and an elastomer including a 1,2-vinyl group. The thermosetting composition is liquid and has a property of turning, when cured thermally, into a cured product having a relative dielectric constant of 3.2 or less at 25° C. and a dielectric loss tangent of 0.013 or less at 25° C.

A semiconductor-mounted product includes a semiconductor package, a wiring substrate, four or more soldered portions, and a resin-reinforced portion. Each of the soldered portions electrically connects the semiconductor package to the wiring of the wiring substrate. The resin-reinforced portion is formed on a side surface of each of the soldered portions. Each of the soldered portions has a first solder region formed closer to the semiconductor package than the wiring substrate and a second solder region formed closer to the wiring substrate than the semiconductor package. A proportion of a void present in a polygon connecting centers of soldered portions located at outermost positions among the soldered portions to a sum of the void and the resin-reinforced portion is from 10% to 99%, inclusive.

A semiconductor-mounted product includes a semiconductor package, a wiring substrate, four or more soldered portions, and a resin-reinforced portion. Each of the soldered portions electrically connects the semiconductor package to the wiring of the wiring substrate. The resin-reinforced portion is formed on a side surface of each of the soldered portions. Each of the soldered portions has a first solder region formed closer to the semiconductor package than the wiring substrate and a second solder region formed closer to the wiring substrate than the semiconductor package. A proportion of a void present in a polygon connecting centers of soldered portions located at outermost positions among the soldered portions to a sum of the void and the resin-reinforced portion is from 10% to 99%, inclusive.

A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.

A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.

A semiconductor device includes a semiconductor substrate configured to include a first electrode layer, and a first barrier layer provided on the first electrode layer and bonded to a metal layer, and a circuit substrate configured to include a second electrode layer, and a second barrier layer provided on the second electrode layer and bonded to the metal layer, wherein the semiconductor substrate including a semiconductor element, and the circuit substrate are bonded via the metal layer containing Sn, a linear expansion coefficient of the first barrier layer is larger than that of the circuit substrate, and a linear expansion coefficient of the second barrier layer is smaller than that of the circuit substrate.

A semiconductor device includes a semiconductor substrate configured to include a first electrode layer, and a first barrier layer provided on the first electrode layer and bonded to a metal layer, and a circuit substrate configured to include a second electrode layer, and a second barrier layer provided on the second electrode layer and bonded to the metal layer, wherein the semiconductor substrate including a semiconductor element, and the circuit substrate are bonded via the metal layer containing Sn, a linear expansion coefficient of the first barrier layer is larger than that of the circuit substrate, and a linear expansion coefficient of the second barrier layer is smaller than that of the circuit substrate.

A micro LED display panel includes a substrate, a plurality of first metal electrodes and a plurality of metal pads on a surface of the substrate, a connection layer on the substrate, a plurality of micro LEDs on a side of the connection layer away from the substrate. The connection layer includes conductive particles. Each of the micro LEDs is coupled to at least one of the first metal electrode. A side of each of the metal pads away from the substrate is coupled to some of the conductive particles in the connection layer to form a metal retaining wall. The metal retaining walls enhance structural strength of the micro LED display panel and avoid breakage of any of the micro LEDs.

A micro LED display panel includes a substrate, a plurality of first metal electrodes and a plurality of metal pads on a surface of the substrate, a connection layer on the substrate, a plurality of micro LEDs on a side of the connection layer away from the substrate. The connection layer includes conductive particles. Each of the micro LEDs is coupled to at least one of the first metal electrode. A side of each of the metal pads away from the substrate is coupled to some of the conductive particles in the connection layer to form a metal retaining wall. The metal retaining walls enhance structural strength of the micro LED display panel and avoid breakage of any of the micro LEDs.

A semiconductor device includes a package substrate, a semiconductor chip and a solder bump. The semiconductor chip is disposed on the package substrate. The package substrate includes a first electrode pad, and a first insulating film formed such that the first insulating film exposes a first portion of a surface of the first electrode pad. The semiconductor chip includes a second electrode pad and a second insulating film formed such that the second insulating film exposes a second portion of a surface of the second electrode pad. The second electrode pad is formed on the first electrode pad through the solder bump. L2/L1 is 0.63 or more in a cross section passing through the first electrode pad, the solder bump and the second electrode pad. A first length of the first portion and a second length of the second portion are defined as L1 and L2, respectively.