A method for manufacturing a display panel includes providing a backplate, forming bonding parts on backplate, forming an auxiliary layer on backplate, releasing light-emitting elements onto the auxiliary layer such that electrodes of the light-emitting elements are in contact with the first parts to form an intermediate backplate, arranging the intermediate backplate under first predetermined condition under which a fluidity of the first part is greater than that of the second part, and bonding the electrodes and the bonding parts to form an eutectic bonding layer, and arranging the intermediate backplate under second predetermined condition such that the first and second parts form solid-state first and second members. The backplate includes first and second regions. The bonding parts are located in the first regions. The auxiliary layer covers the backplate and the bonding parts. The auxiliary layer includes first and second parts respectively located in the first and second regions.

A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

A display panel includes a pixel array substrate, a plurality of vertical light emitting devices and a flip-chip light emitting device. The pixel array substrate has a first pixel area and a second pixel area. The vertical light emitting devices are disposed in the first pixel area and the second pixel area and electrically connected to the pixel array substrate. The flip-chip light emitting device is disposed in the second pixel area and electrically connected to the pixel array substrate. A color of an emitted light beam of the flip-chip light emitting device and a color of an emitted light beam of one of the vertical light emitting devices located in the first pixel area are identical.

The present invention discloses a method for packaging a chip-on-film (COF). The method includes: S1, forming a plurality of first pins on a circuit surface of a flexible circuit substrate, and forming a plurality of second pins on a chip to be packaged; S2, arranging to keep the circuit surface always facing downwards, arranging to keep a surface of the chip to be packaged, where the second pins matching the first pins are arranged, always facing upwards, and arranging the first pins and the second pins, to be opposite to each other; and S3, applying a top-down pressure to the flexible circuit substrate, and/or applying a bottom-up pressure to the chip to be packaged, and simultaneously heating at high temperature to solder the first pins and the second pins in a fused eutectic manner. The method of the present invention improves the product yield and stability.

A light emitting device includes: a plurality of element structural bodies, each including: a substrate, a light emitting element mounted on or above the substrate, and a light-transmissive member disposed on or above the light emitting element, wherein at least three of the plurality of element structural bodies are disposed along a first direction; a first covering member that covers lateral surfaces of the substrate, the light emitting element, and the light-transmissive member of each of the plurality of element structural bodies; and a support member that covers a lateral surface of the first covering member, wherein at least a portion of the support member is disposed lateral to the plurality of element structural bodies and extends along the first direction. A rigidity of the support member is greater than a rigidity of the first covering member.

A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.

A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

A semiconductor package includes a first semiconductor component, a second semiconductor component, and a connecting element. The first semiconductor component includes a first substrate, and a first bonding pad disposed adjacent to a first surface of the first substrate, and at least one conductive via structure extending from a second surface of the first substrate to the first bonding pad. The second semiconductor component includes a second substrate, a redistribution layer disposed adjacent to a first surface of the second substrate, and a second bonding pad disposed on the redistribution layer. The connecting element is disposed between the first bonding pad and the second bonding pad.