A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.

A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.

A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

A package that includes a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the first integrated device. A portion of the second integrated device overhangs over the first integrated device. The second integrated device is configured to be coupled to the substrate. The second integrated device includes a front side and a back side. The front side of the second integrated device faces the substrate.

In one example, a semiconductor device, includes a substrate having a substrate top side, a substrate bottom side, a substrate dielectric structure, and a substrate conductive structure. The substrate conductive structure includes a transceiver pattern proximate to a substrate top side. An antenna structure includes an antenna dielectric structure coupled to the substrate top side, an antenna conductive structure having an antenna element, and a cavity below the antenna element. The antenna element overlies the transceiver pattern. The cavity includes a cavity ceiling, a cavity base, and a cavity sidewall between the cavity ceiling and the cavity base. Either a bottom surface of the antenna element defines the cavity ceiling and a perimeter portion of the antenna element is fixed to the antenna dielectric structure, or the antenna dielectric structure includes a body portion having a bottom surface that defines the cavity ceiling and the antenna element is vertically spaced apart from the bottom surface of the body portion. An semiconductor component is coupled to a bottom side of the substrate and is coupled to the transceiver pattern. Other examples and related methods are also disclosed herein.

An electronic device, a package structure and an electronic manufacturing method are provided. The electronic device includes a substrate, a first bump, a second bump and a first reflowable material. The first bump is disposed over the substrate, and has a first width. An end portion of the first bump defines a first recess portion. The second bump is disposed over the substrate, and has a second width less than the first width. The first reflowable material is disposed on the first bump and extends in the first recess portion.

A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a redistribution layer (RDL) structure, a passive device, and a plurality of dummy items. The encapsulant laterally encapsulates the die. The RDL structure is disposed on the die and the encapsulant. The passive device is disposed on and electrically bonded to the RDL structure. The plurality of dummy items are disposed on the RDL structure and laterally aside the passive device, wherein top surfaces of the plurality of dummy items are higher than a top surface of the passive device.

Embodiments disclose a package structure and a fabricating method. The package structure includes: a semiconductor chip; a first non-conductive layer covering a front surface of the semiconductor chip and part of a side wall of the semiconductor chip; a second non-conductive layer positioned on an upper surface of the first non-conductive layer and covering at least part of a side wall of the first non-conductive layer, wherein a melt viscosity of the first non-conductive layer is greater than a melt viscosity of the second non-conductive layer; a substrate; and a solder mask layer positioned on a surface of the substrate, where a first opening is provided in the solder mask layer. The semiconductor chip is flip-chip bonded on the substrate, a surface of the second non-conductive layer away from the first non-conductive layer and a surface of the solder mask layer away from the substrate are bonding surfaces.

A package structure is provided. The package structure includes a reinforced plate and multiple conductive structures penetrating through the reinforced plate. The package structure also includes a redistribution structure over the reinforced plate. The redistribution structure has multiple polymer-containing layers and multiple conductive features. The package structure further includes multiple chip structures bonded to the redistribution structure through multiple solder bumps. In addition, the package structure includes a protective layer surrounding the chip structures.