A fluxless bonding process is provided. An array of micro solder bumps of a first semiconductor structure is aligned to an array of bonding pads of a second semiconductor structure under an applied bonding force. An environment is provided to prevent oxides from forming on the solder bump structures and bonding pads during the bonding process. A scrubbing process is performed at a given scrubbing frequency and amplitude to scrub the micro solder bumps against the bonding pads in a direction perpendicular to the bonding. Heat is applied to at least the first semiconductor structure to melt and bond the micro solder bumps to the bonding pads. The first semiconductor structure is cooled down to solidify the molten solder. Coplanarity is maintained between the bonding surfaces of the semiconductor structures within a given tolerance during the scrubbing and cooling steps until solidification of the micro solder bumps.

A package structure is provided, in which a second electronic element having a plurality of conductive bumps is stacked on a first electronic element arranged with a positioning layer. The plurality of conductive bumps are inserted into a plurality of positioning holes of the positioning layer, and the second electronic element is bonded onto the positioning layer and electrically connected to the first electronic element via the plurality of conductive bumps, such that the hybrid bonding technology is replaced via the arrangement of the positioning holes and the conductive bumps, thereby reducing packaging costs.

Disclosed technology provides a solder ball including an outer layer having a first conductive material that is solid at an operating temperature of an electronic device, and an inner region having a second conductive material that flows at the operating temperature of the electronic device, wherein the inner region is surrounded by the outer layer. A method of manufacturing a solder ball includes forming an outer layer comprising a first conductive material that is solid at an operating temperature of an electronic device, wherein the outer layer surrounds an inner region, introducing a hole into the outer layer, injecting a second conductive material through the hole of the outer layer into the inner region, wherein the second conductive material flows at the operating temperature of the electronic device, and sealing the hole of the outer layer such that the second conductive material is retained within the inner region.

A method of packaging a chip includes: forming a groove on a circuit board. Providing a chip assembly, the chip assembly includes the chip, conductive pastes, and a deformable member. Placing the chip assembly at a first temperature to cause the deformable member to contract. Placing the chip assembly in the groove; heating the chip assembly at a second temperature. Subjecting the circuit board and the chip assembly to reflow soldering at a third temperature. The third temperature is greater than the second temperature, and the second temperature is greater than the first temperature. The present disclosure further provides a chip packaging structure and a terminal device.

A method for fabricating a semiconductor package includes applying polymer-based solder paste onto a substrate; bringing a plurality of solder bumps on a semiconductor die into contact with the polymer-based solder paste on the substrate; reflowing the polymer-based solder paste to form a plurality of solder joints between the substrate and the semiconductor die, wherein a post-soldering residue is produced to encapsulate a lower portion of each solder joint; and applying an underfill between the substrate and the semiconductor die to encapsulate an upper portion of the solder joint.

A connecting structure includes a first substrate having a plurality of first electrodes arranged in a plane direction; a second substrate having a plurality of second electrodes arranged in the plane direction and disposed at a spaced interval with respect to the first substrate in a thickness direction perpendicular to the plane direction so that the first electrode faces the second electrode; and an adhesive layer interposed between the first substrate and the second substrate, electrically connecting the first electrode and the second electrode facing each other in the thickness direction, and adhering the first substrate to the second substrate. A thickness of the adhesive layer is below 15 m. A distance A between the first electrodes adjacent to each other In the plane direction is longer than a distance B between the first electrode and the second electrode facing each other in the thickness direction.

A method includes forming a redistribution structure over a carrier, attaching a semiconductor die to the redistribution structure using first conductive connectors, dispensing a first underfill into a first gap between the semiconductor die and the redistribution structure, bonding a substrate to the redistribution structure using second conductive connectors, the substrate being bonded to an opposing side of the redistribution structure as the semiconductor die, and attaching a ring to the substrate, where the ring surrounds the semiconductor die and the first underfill, and where the ring includes a first portion that includes a first material having a first co-efficient of thermal expansion, and second portions that include a second material having a second co-efficient of thermal expansion that is different from the first co-efficient of thermal expansion.

A method includes forming a redistribution structure over a carrier, attaching a semiconductor die to the redistribution structure using first conductive connectors, dispensing a first underfill into a first gap between the semiconductor die and the redistribution structure, bonding a substrate to the redistribution structure using second conductive connectors, the substrate being bonded to an opposing side of the redistribution structure as the semiconductor die, and attaching a ring to the substrate, where the ring surrounds the semiconductor die and the first underfill, and where the ring includes a first portion that includes a first material having a first co-efficient of thermal expansion, and second portions that include a second material having a second co-efficient of thermal expansion that is different from the first co-efficient of thermal expansion.

A semiconductor device includes: a terminal having a connection surface facing one side in a first direction; a semiconductor element electrically connected to the connection surface; and a sealing resin covering a portion of the terminal and the semiconductor element, wherein the terminal is located on the other side in the first direction with respect to the connection surface and has a first surface recessed into the terminal and a second surface connected to the connection surface and the first surface, wherein the first surface overlaps the connection surface when viewed in the first direction, and wherein the second surface is convex and is in contact with the sealing resin.

A semiconductor device includes a lower substrate. A first pad is disposed on the lower substrate. An upper substrate is disposed on the lower substrate. A second pad is disposed in a lower portion of the upper substrate. A solder structure is disposed between the first pad and the second pad. A coating layer covers at least a portion of an external surface of the solder structure. The solder structure includes a first portion disposed on a first surface that is in contact with the first pad. The first portion has a first solder pattern and a second solder pattern. The second solder pattern surrounds the first solder pattern.