Electronic assembly methods and structures are described. In an embodiment, an electronic assembly method includes bringing together an electronic component and a routing substrate, and directing a large area photonic soldering light pulse toward the electronic component to bond the electronic component to the routing substrate.

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.

A method of manufacturing component carriers includes carrying out a test for each of multiple sections of a component-carrier structure, inserting at least one functional component in each of further sections of a further component-carrier structure to be connected with the component-carrier structure so that each further section assigned to a respective section having successfully passed the test is provided with at least one functional component, and inserting at least one functionally inactive dummy component in each of the further sections assigned to a respective section having failed the test.

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

A module structure comprises a patterned substrate having a substrate surface and comprising a substrate post protruding from the substrate surface. A component is disposed on the substrate post. The component has a component top side and a component bottom side opposite the component top side. The component bottom side is disposed on the substrate post. The component extends over at least one edge of the substrate post. One or more component electrodes are disposed on the component.

A module structure comprises a patterned substrate having a substrate surface and comprising a substrate post protruding from the substrate surface. A component is disposed on the substrate post. The component has a component top side and a component bottom side opposite the component top side. The component bottom side is disposed on the substrate post. The component extends over at least one edge of the substrate post. One or more component electrodes are disposed on the component.

A cavity structure comprises a cavity substrate comprising a substrate surface, one or more cavity walls extending from the substrate surface, a cap disposed on the one or more cavity walls, and at least a portion of a module tether physically attached to the cavity substrate. The cavity substrate, the cap, and the one or more cavity walls form a cavity enclosing a volume, for example enclosing a vacuum, air, an added gas, or a liquid. The cavity structure can be a micro-transfer printable structure provided on a cavity structure source wafer. A plurality of cavity structures can be disposed on a destination substrate, for example by transfer printing, dry contact printing, or micro-transfer printing.

A cavity structure comprises a cavity substrate comprising a substrate surface, one or more cavity walls extending from the substrate surface, a cap disposed on the one or more cavity walls, and at least a portion of a module tether physically attached to the cavity substrate. The cavity substrate, the cap, and the one or more cavity walls form a cavity enclosing a volume, for example enclosing a vacuum, air, an added gas, or a liquid. The cavity structure can be a micro-transfer printable structure provided on a cavity structure source wafer. A plurality of cavity structures can be disposed on a destination substrate, for example by transfer printing, dry contact printing, or micro-transfer printing.

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, a cap layer, a conductive terminal, and a dam structure. The semiconductor die has a first surface. The cap layer is over the semiconductor die and has a second surface facing the first surface of the semiconductor die. The conductive terminal penetrates the cap layer and electrically connects to the semiconductor die. The dam structure is between the semiconductor die and the cap layer and surrounds a portion of the conductive terminal between the first surface and the second surface, thereby forming a gap between the cap layer and the semiconductor die.