A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.

A method comprises: providing a layer of curable adhesive material (4) on a substrate (2); forming a pattern of microstructures (321) on the layer of curable adhesive material (4); curing a first region (42) of the layer of curable adhesive material (4) at a first level and a second region (44) of the layer of curable adhesive material (4) at a second level greater than the first level; providing a solid circuit die (6) to directly attach to a major surface of the first region (42) of the layer of curable adhesive material (4); and further curing the first region (42) of the layer of curable adhesive material (4) to anchor the solid circuit die (6) on the first region (42) by forming an adhesive bond therebetween. The pattern of microstructures (321) may include one or more microchannels (321), the method further comprising forming one or more electrically conductive traces in the microchannels (321), in particular, by flow of a conductive particle containing liquid (8) by a capillary force and, optionally, under pressure. The at least one microchannel (321) may extend from the second region (44) to the first region (42) and have a portion beneath the solid circuit die (6). The solid circuit die (6) may have at least one edge disposed within a periphery of the first region (42) with a gap therebetween. The solid circuit die (6) may have at least one contact pad (72) on a bottom surface thereof, wherein the at least one contact pad (72) may be in direct contact with at least one of the electrically conductive traces in the microchannels (321). Forming the pattern of microstructures (321) may comprise contacting a major surface of a stamp (3) to the layer of curable adhesive material (4), the major surface having a pattern of raised features (32) thereon. The curable adhesive material (4) may be cured by an actinic light source such as an ultraviolet (UV) light source (7, 7), wherein a mask may be provided to at least partially block the first region (42) of the layer of curable adhesive material (4) from the cure. The stamp (3) may be positioned in contact with the curable adhesive material (4) to replicate the pattern of raised features (32) to form the microstructures (321) while the curable adhesive material (4) is selectively cured by the actinic light source such as the ultraviolet (UV) light source (7). The first region (42) of the layer of curable

A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

A patterned, non-conductive substrate for an integrated circuit (IC) package has a die side configured to receive a die and a lead side opposite the die side. A pattern formed in the substrate defines openings (e.g., holes, steps, grooves, and/or cavities) that extend between the die side and the lead side of the substrate. In the IC package, the openings are filled with conductive material (e.g., solder) that supports electrical connections between bond pads on the die and leads formed from the conductive material. The substrate can be used to form a relatively inexpensive, quad flat no-lead (QFN) IC package without using a metal lead frame and without bond wires.

A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

A patterned, non-conductive substrate for an integrated circuit (IC) package has a die side configured to receive a die and a lead side opposite the die side. A pattern formed in the substrate defines openings (e.g., holes, steps, grooves, and/or cavities) that extend between the die side and the lead side of the substrate. In the IC package, the openings are filled with conductive material (e.g., solder) that supports electrical connections between bond pads on the die and leads formed from the conductive material. The substrate can be used to form a relatively inexpensive, quad flat no-lead (QFN) IC package without using a metal lead frame and without bond wires.

A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

A packaged integrated circuit (IC) includes a substrate including a first substrate pad disposed on a first side of the substrate, an IC die disposed on the first side of the substrate, and a first insulating layer molded over the IC die and the substrate. The IC die includes a first die pad on a side of the die opposite from a side of the die adjacent to the first side of the substrate. The first insulating layer includes a first channel extending through the first insulating layer to the first substrate pad, a second channel extending through the first insulating layer to the first die pad, conductive paste filling the first channel and in contact with the first substrate pad, and conductive paste filling the second channel and in contact with the die pad.

In described examples of a circuit module, a multilayer substrate has a conductive pad formed on a surface of the multilayer substrate. An integrated circuit (IC) die is bonded to the surface of the substrate in dead bug manner, such that a set of bond pads formed on a surface of the IC die are exposed. A planar interconnect line formed by printed ink couples the set of bond pads to the conductive pad.