An electronic assembly is disclosed. The electronic assembly includes a primary die, comprising a bulk layer, an integrated circuitry layer, a metal layer, a first redistribution layer, and a first attachment layer. The primary die further includes at least one aligned through-hole in the bulk layer and integrated circuitry layer. The electronic assembly further includes a secondary die physically coupled to the primary die via a second attachment layer. The electronic assembly further includes an interconnect header that includes plurality of interconnect filaments configured to electrically couple the first redistribution layer to one of the at least one metal layer via the at least one bulk layer through-hole and the at least one integrated circuitry through-hole. The interconnect header is generated by applying an electrically conductive filaments on a plurality of wafers, thinning the wafers, stacking and attaching the wafers into a wafer stack, and dicing the wafer stack.

The present application provides a method for forming a chip package and a chip package. The method comprises mounting at least one chipset including at least first and second chips on a carrier with front surface of the chips face away from the carrier; attaching an interconnection device to the front surfaces of the first and second chips to enable electrically connections between the chips; forming a molded encapsulation layer whereby the first chip, the second chip and the interconnection device are embedded or partially embedded in the molded encapsulation layer; thinning one side of the molded encapsulation layer away from the carrier to expose first bumps on the first and second chips; forming second bumps on a surface of one side of the molded encapsulation layer where the first bumps are exposed; and removing the carrier. Thus, a flexible, efficient and low-cost packaging scheme is provided for multi-chip connection.

The present application provides a method for forming chip packages and a chip package. The method comprises arranging a plurality of interconnect devices at intervals on a surface of a carrier and assembling a plurality of chipsets over the interconnect devices. Each chipset comprises at least two chips electrically connected through an interconnect device. A front surface of each chip facing the carrier is provided with a plurality of first bumps. The method further comprises forming a molded package layer whereby the plurality of chipsets and the plurality of interconnect devices are embedded in the molded package layer; removing the carrier and thinning the molded package layer to expose the first bumps; forming second bumps on the surface on one side of the molded package layer where the first bumps are exposed; and dicing the molded package layer to obtain a plurality of package units. Thus, a flexible and low-cost packaging scheme is provided for multi-chip interconnection.

Methods and structures for forming arrays of LED devices are disclosed. The LED devices in accordance with embodiments of the invention may include an internally confined current injection area to reduce non-radiative recombination due to edge effects. Several manners for confining current may include etch removal of a current distribution layer, etch removal of a current distribution layer and active layer followed by mesa re-growth, isolation by ion implant or diffusion, quantum well intermixing, and oxide isolation.

An electronic module on a flexible planar circuit substrate with a conductor configuration on a first substrate surface and a plurality of electronic components on the opposite, second substrate surface, wherein the components have component contacts, which are electrically connected selectively by way of vias in the circuit substrate and the conductor configuration, wherein the circuit substrate is a thermoplastic polymer and the component contacts are melted or thermally pressed into the second substrate surface in the region of the vias.

Methods and structures for forming arrays of LED devices are disclosed. The LED devices in accordance with embodiments of the invention may include an internally confined current injection area to reduce non-radiative recombination due to edge effects. Several manners for confining current may include etch removal of a current distribution layer, etch removal of a current distribution layer and active layer followed by mesa re-growth, isolation by ion implant or diffusion, quantum well intermixing, and oxide isolation.

Methods and structures for forming arrays of LED devices are disclosed. The LED devices in accordance with embodiments of the invention may include an internally confined current injection area to reduce non-radiative recombination due to edge effects. Several manners for confining current may include etch removal of a current distribution layer, etch removal of a current distribution layer and active layer followed by mesa re-growth, isolation by ion implant or diffusion, quantum well intermixing, and oxide isolation.

Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly comprises a die stack including a plurality of semiconductor dies, and a routing substrate mounted on the die stack. The routing substrate includes an upper surface having a redistribution structure. The semiconductor assembly also includes a plurality of electrical connectors coupling the redistribution structure to at least some of the semiconductor dies. The semiconductor assembly further includes a controller die mounted on the routing substrate. The controller die includes an active surface that faces the upper surface of the routing substrate and is electrically coupled to the redistribution structure, such that the routing substrate and the semiconductor dies are electrically coupled to the controller die via the redistribution structure.

Methods and structures for forming arrays of LED devices are disclosed. The LED devices in accordance with embodiments of the invention may include an internally confined current injection area to reduce non-radiative recombination due to edge effects. Several manners for confining current may include etch removal of a current distribution layer, etch removal of a current distribution layer and active layer followed by mesa re-growth, isolation by ion implant or diffusion, quantum well intermixing, and oxide isolation.

An embodiment includes an apparatus comprising: a first device layer included in a top edge of a semiconductor substrate; metal layers, on the first device layer, including first and second metal layers; a second device layer on the metal layers; and additional metal layers on the second device layer; wherein the second device layer is not included in any semiconductor substrate. Other embodiments are described herein.