The present invention: makes it possible to improve the reliability of a semiconductor device; and provides a method of manufacturing the semiconductor device comprising the steps of (a) providing a semiconductor wafer having a pad electrode, a first conductive layer comprised of copper, a photoresist film, and a second conductive layer comprised of gold, (b) forming a protective film comprised of iodine on the surface of the second conductive layer, (c) removing the photoresist film, (d) irradiating the protective film with argon ions and removing the protective film, and (e) bringing a part of a bonding wire into contact with the surface of the second conductive layer.

An integrated circuit package and methods for packaging an integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first die and the palladium coated copper wires. The first die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.

An object of the present invention is to improve the degree of freedom in the wiring design of a wiring substrate configuring a semiconductor device. Lands having an NSMD structure and a land-on-through-hole structure are arranged at positions not overlapping with a plurality of leads arranged on a chip loading surface of a wiring substrate in transparent plan view on the outer peripheral side of a mounting surface of the wiring substrate configuring a semiconductor device having a BGA package structure. On the other hand, land parts having the NSMD structure and to which lead-out wiring parts are connected are arranged at positions overlapping with the leads arranged on the chip loading surface of the wiring substrate in transparent plan view on the inner side than the group of lands in the mounting surface of the wiring substrate.

The semiconductor device of the present invention is a semiconductor device in which a first semiconductor chip including a first field effect transistor for a high-side switch, a second semiconductor chip including a second field effect transistor for a low-side switch, and a third semiconductor chip including a circuit that controls each of the first and second semiconductor chips are sealed with a sealing portion. A lead electrically connected to a pad of the first semiconductor chip for a source of the first field effect transistor and a lead electrically connected to a back-surface electrode of the second semiconductor chip for a drain of the second field effect transistor are disposed on the same side of the sealing portion in a plan view.

According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.

The present invention: makes it possible to improve the reliability of a semiconductor device; and provides a method of manufacturing the semiconductor device comprising the steps of (a) providing a semiconductor wafer having a pad electrode, a first conductive layer comprised of copper, a photoresist film, and a second conductive layer comprised of gold, (b) forming a protective film comprised of iodine on the surface of the second conductive layer, (c) removing the photoresist film, (d) irradiating the protective film with argon ions and removing the protective film, and (e) bringing a part of a bonding wire into contact with the surface of the second conductive layer.

An object of the present invention is to improve the degree of freedom in the wiring design of a wiring substrate configuring a semiconductor device. Lands having an NSMD structure and a land-on-through-hole structure are arranged at positions not overlapping with a plurality of leads arranged on a chip loading surface of a wiring substrate in transparent plan view on the outer peripheral side of a mounting surface of the wiring substrate configuring a semiconductor device having a BGA package structure. On the other hand, land parts having the NSMD structure and to which lead-out wiring parts are connected are arranged at positions overlapping with the leads arranged on the chip loading surface of the wiring substrate in transparent plan view on the inner side than the group of lands in the mounting surface of the wiring substrate.

Methods, systems and devices are disclosed for performing a semiconductor processing operation. In some embodiments this includes configuring a wire bonding machine to perform customized movements with a capillary tool of the wire bonding machine, etching bulk contaminants over one or more locations of a semiconductor device with the capillary tool, and applying plasma to the semiconductor device to remove residual contaminants.

The semiconductor device of the present invention is a semiconductor device in which a first semiconductor chip including a first field effect transistor for a high-side switch, a second semiconductor chip including a second field effect transistor for a low-side switch, and a third semiconductor chip including a circuit that controls each of the first and second semiconductor chips are sealed with a sealing portion. A lead electrically connected to a pad of the first semiconductor chip for a source of the first field effect transistor and a lead electrically connected to a back-surface electrode of the second semiconductor chip for a drain of the second field effect transistor are disposed on the same side of the sealing portion in a plan view.

Disclosed is a semiconductor package comprising a substrate that includes bonding pads on an upper edge of the substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip, a plurality of bonding wires configured to connect the second semiconductor chip to the bonding pads, a plurality of dam structures on the substrate and between the first semiconductor chip and the bonding pads, and a molding member on the plurality of dam structures, the substrate, the first semiconductor chip, and the second semiconductor chip. The plurality of dam structures includes a first dam structure having a closed loop shape that extends around the first semiconductor chip, and a second dam structure between the first dam structure and the bonding pads.