Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.

A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only.

Aspects of the disclosure relate generally to semiconductor packaging, and specifically to semiconductor device having a lead frame having a semiconductor supporting die pad that is capable of engaging with a wire bonding clamp.

Semiconductor devices include a plurality of gate fingers extending on a wide bandgap semiconductor layer structure. An inter-metal dielectric pattern is formed on the gate fingers, the inter-metal dielectric pattern including a plurality of dielectric fingers that cover the respective gate fingers. A top-side metallization is provided on the inter-metal dielectric pattern and on exposed portions of the upper surface of the wide bandgap semiconductor layer structure. The top-side metallization includes a first conductive diffusion barrier layer on the inter-metal dielectric pattern and on the exposed portions of the upper surface of the wide bandgap semiconductor layer structure, a conductive contact layer on an upper surface of the first conductive diffusion barrier layer, and a grain stop layer buried within the conductive contact layer.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 m in thickness.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 m in thickness.

A semiconductor device, a drain electrode terminal supporting the semiconductor device and connected directly to a drain electrode pad, a source electrode terminal connected to a source electrode pad, and a gate electrode terminal are provided, wherein the source electrode terminal includes a wire post, a first lead extending from one end of the wire post, and a second lead extending from another end of the wire post, wherein the source electrode pad and the wire post of the source electrode terminal are connected to each other through a plurality of bonding wires, and wherein the semiconductor device, a surface, supporting the semiconductor device thereon, of the drain electrode terminal, the wire post of the source electrode terminal, the bonding wires, and part of the gate electrode terminal are covered with a mold resin.

A semiconductor device, a drain electrode terminal supporting the semiconductor device and connected directly to a drain electrode pad, a source electrode terminal connected to a source electrode pad, and a gate electrode terminal are provided, wherein the source electrode terminal includes a wire post, a first lead extending from one end of the wire post, and a second lead extending from another end of the wire post, wherein the source electrode pad and the wire post of the source electrode terminal are connected to each other through a plurality of bonding wires, and wherein the semiconductor device, a surface, supporting the semiconductor device thereon, of the drain electrode terminal, the wire post of the source electrode terminal, the bonding wires, and part of the gate electrode terminal are covered with a mold resin.

A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.

A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.