A wafer uniting method includes a thermocompression bonding step of causing a thermocompression bonding sheet having a size comparable to or greater than a size and a shape of a wafer and a front surface of the wafer to face each other, and pressing them against each other while applying heat to thermocompression bond the thermocompression bonding sheet to the front surface of the wafer. The thermocompression bonding sheet thermocompression bonded to the wafer in the thermocompression bonding step includes at least a first thermocompression bonding sheet and a second thermocompression bonding sheet.

A ribbon bonding tool is provided. The ribbon bonding tool includes a body portion including a tip portion, the tip portion defining a working surface. The ribbon bonding tool includes a group of four protrusions extending from the working surface, wherein the working surface defines four quadrants in a horizontal plane by extending an imaginary line at a midpoint along each of a length and a width of the working surface. Each of the four protrusions is arranged in one of four quadrants.

A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire that is bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. An area of a part of the bonding surface, the part not overlapping the wire, is small.

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna, each of the five sections or segments forming a pair of angles with each adjacent segment or section, wherein the smaller angle of each of the four pairs of angles between sections or segments is less than 180 (i.e., no pair of sections or segments define a longer straight segment), wherein at least two of the angles are less than 115, wherein at least two of the angles are not equal, and wherein the curve fits inside a rectangular area the longest edge of which is shorter than one-fifth of the longest free-space operating wavelength of the antenna.

The present disclosure provides a package structure, including a semiconductor chip having a magnetic device, wherein the semiconductor chip includes a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface, and a third surface connecting the first surface and the second surface, and a first magnetic field shielding at least partially surrounding the third surface.

The present disclosure provides a package structure, including a semiconductor chip having a magnetic device, wherein the semiconductor chip includes a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface, and a third surface connecting the first surface and the second surface, and a first magnetic field shielding at least partially surrounding the third surface.

There is provided a bonding wire for a semiconductor device including a coating layer having Pd as a main component on a surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on a surface of the coating layer, the bonding wire further improving 2nd bondability on a Pd-plated lead frame and achieving excellent ball bondability even in a high-humidity heating condition. The bonding wire for a semiconductor device including the coating layer having Pd as a main component on the surface of the Cu alloy core material and the skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing either or both of Pd and Pt in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in the 2nd bondability and excellent ball bondability in the high-humidity heating condition. Furthermore, a maximum concentration of Au in the skin alloy layer is preferably 15 at % to 75 at %.

There is provided a bonding wire for a semiconductor device including a coating layer having Pd as a main component on a surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on a surface of the coating layer, the bonding wire further improving 2nd bondability on a Pd-plated lead frame and achieving excellent ball bondability even in a high-humidity heating condition. The bonding wire for a semiconductor device including the coating layer having Pd as a main component on the surface of the Cu alloy core material and the skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing either or both of Pd and Pt in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in the 2nd bondability and excellent ball bondability in the high-humidity heating condition. Furthermore, a maximum concentration of Au in the skin alloy layer is preferably 15 at % to 75 at %.

A method to produce a substrate suitable for diffusion bonding is described. A flexible dielectric substrate is provided. An alkaline modification is applied to the dielectric substrate to form a polyamic acid (PAA) anchoring layer on a surface of the dielectric substrate. A NiP seed layer is electrolessly plated on the PAA layer. Copper traces are plated within a photoresist pattern on the NiP seed layer. A surface finishing layer is electrolytically plated on the copper traces. The photoresist pattern and NiP seed layer not covered by the copper traces are removed to complete the substrate suitable for diffusion bonding.

An embodiment method includes encapsulating a semiconductor die in an encapsulant, planarizing the encapsulant, and depositing a polymer material on the encapsulant. The method further includes planarizing the polymer material and forming a metallization pattern on the polymer material. The metallization pattern electrically connects a die connector of the semiconductor die to a conductive feature disposed outside of the semiconductor die.