There is provided a bonding wire for a semiconductor device including a coating layer having Pd as a main component on a surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on a surface of the coating layer, the bonding wire further improving 2nd bondability on a Pd-plated lead frame and achieving excellent ball bondability even in a high-humidity heating condition. The bonding wire for a semiconductor device including the coating layer having Pd as a main component on the surface of the Cu alloy core material and the skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing either or both of Pd and Pt in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in the 2nd bondability and excellent ball bondability in the high-humidity heating condition. Furthermore, a maximum concentration of Au in the skin alloy layer is preferably 15 at % to 75 at %.

There is provided a bonding wire for a semiconductor device including a coating layer having Pd as a main component on a surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on a surface of the coating layer, the bonding wire further improving 2nd bondability on a Pd-plated lead frame and achieving excellent ball bondability even in a high-humidity heating condition. The bonding wire for a semiconductor device including the coating layer having Pd as a main component on the surface of the Cu alloy core material and the skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing either or both of Pd and Pt in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in the 2nd bondability and excellent ball bondability in the high-humidity heating condition. Furthermore, a maximum concentration of Au in the skin alloy layer is preferably 15 at % to 75 at %.

A method to produce a substrate suitable for diffusion bonding is described. A flexible dielectric substrate is provided. An alkaline modification is applied to the dielectric substrate to form a polyamic acid (PAA) anchoring layer on a surface of the dielectric substrate. A NiP seed layer is electrolessly plated on the PAA layer. Copper traces are plated within a photoresist pattern on the NiP seed layer. A surface finishing layer is electrolytically plated on the copper traces. The photoresist pattern and NiP seed layer not covered by the copper traces are removed to complete the substrate suitable for diffusion bonding.

A semiconductor device of an embodiment includes a substrate including a semiconductor element, a first electrode on the substrate and electrically connected to the semiconductor element, a second electrode on the substrate and electrically connected to the semiconductor element, and a terminal spaced from the first electrode, the substrate, and the second electrode. A first bonding wire has a first bonding portion bonded to the second electrode at a first end and a second bonding portion bonded to the terminal at a second end. A second bonding wire has a third bonding portion bonded to the second electrode at a first end and a fourth bonding portion bonded to the terminal at a second end. Each of the first and second bonding wires comprise copper and have a diameter less than or equal to 100 m.

A semiconductor device of an embodiment includes a substrate including a semiconductor element, a first electrode on the substrate and electrically connected to the semiconductor element, a second electrode on the substrate and electrically connected to the semiconductor element, and a terminal spaced from the first electrode, the substrate, and the second electrode. A first bonding wire has a first bonding portion bonded to the second electrode at a first end and a second bonding portion bonded to the terminal at a second end. A second bonding wire has a third bonding portion bonded to the second electrode at a first end and a fourth bonding portion bonded to the terminal at a second end. Each of the first and second bonding wires comprise copper and have a diameter less than or equal to 100 m.

Provided are a thermal bonding sheet capable of suppressing inhibition of sintering of sinterable metallic particles by an organic component, thereby imparting sufficient bonding reliability to a power semiconductor device, and a thermal bonding sheet with a dicing tape having the thermal bonding sheet. A thermal bonding sheet has a precursor layer that is to become a sintered layer by heating, and the precursor layer has sinterable metallic particles and an organic component, a 95% weight loss temperature of the organic component is 150 C. or more and 300 C. or less when thermogravimetry of the thermal bonding sheet is performed under an air atmosphere at a heating rate of 10 C./min.

Techniques and mechanisms for provide interconnection with integrated circuitry. In an embodiment, a packaged device includes a substrate and one or more integrated circuit (IC) dies. A first conductive pad is formed at a first side of a first IC die, and a second conductive pad is formed at a second side of the substrate or another IC die. Wire bonding couples a wire between the first conductive pad and the second conductive pad, wherein a distal end of the wire is bonded, via a bump, to an adjoining one of the first conductive pad and the second conductive pad. A harness of the bump, which is less than a hardness of the wire, mitigates damage to the adjoining pad that might otherwise occur as a result of wire bonding stresses. In another embodiment, the wire includes copper (Cu) and the bump includes gold (Au) or silver (Ag).

Techniques and mechanisms for provide interconnection with integrated circuitry. In an embodiment, a packaged device includes a substrate and one or more integrated circuit (IC) dies. A first conductive pad is formed at a first side of a first IC die, and a second conductive pad is formed at a second side of the substrate or another IC die. Wire bonding couples a wire between the first conductive pad and the second conductive pad, wherein a distal end of the wire is bonded, via a bump, to an adjoining one of the first conductive pad and the second conductive pad. A harness of the bump, which is less than a hardness of the wire, mitigates damage to the adjoining pad that might otherwise occur as a result of wire bonding stresses. In another embodiment, the wire includes copper (Cu) and the bump includes gold (Au) or silver (Ag).

Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.

A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2).