An apparatus includes a main body having an electrode and a contact element. The contact element is directly mechanically and electrically conductively connected to the electrode in order to form an electrical connection between the main body and the contact element. The electrical and mechanical connection between the electrode and the contact element is free of melting regions of the materials of the electrode and of the contact element that are involved in the connection. Furthermore, the connection is realized in a manner free of connection material, for example, in a manner free of solder material.

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna, each of the five sections or segments forming a pair of angles with each adjacent segment or section, wherein the smaller angle of each of the four pairs of angles between sections or segments is less than 180 (i.e., no pair of sections or segments define a longer straight segment), wherein at least two of the angles are less than 115, wherein at least two of the angles are not equal, and wherein the curve fits inside a rectangular area the longest edge of which is shorter than one-fifth of the longest free-space operating wavelength of the antenna.

Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.

Flexible interconnects, flexible integrated circuit systems and devices, and methods of making and using flexible integrated circuitry are presented herein. A flexible integrated circuit system is disclosed which includes first and second discrete devices that are electrically connected by a discrete flexible interconnect. The first discrete devices includes a first flexible multi-layer integrated circuit (IC) package with a first electrical connection pad on an outer surface thereof. The second discrete device includes a second flexible multi-layer integrated circuit (IC) package with a second electrical connection pad on an outer surface thereof. The discrete flexible interconnect is attached to and electrically connects the first electrical connection pad of the first discrete device to the second electrical connection pad of the second discrete device.

Flexible interconnects, flexible integrated circuit systems and devices, and methods of making and using flexible integrated circuitry are presented herein. A flexible integrated circuit system is disclosed which includes first and second discrete devices that are electrically connected by a discrete flexible interconnect. The first discrete devices includes a first flexible multi-layer integrated circuit (IC) package with a first electrical connection pad on an outer surface thereof. The second discrete device includes a second flexible multi-layer integrated circuit (IC) package with a second electrical connection pad on an outer surface thereof. The discrete flexible interconnect is attached to and electrically connects the first electrical connection pad of the first discrete device to the second electrical connection pad of the second discrete device.

An embodiment method includes encapsulating a semiconductor die in an encapsulant, planarizing the encapsulant, and depositing a polymer material on the encapsulant. The method further includes planarizing the polymer material and forming a metallization pattern on the polymer material. The metallization pattern electrically connects a die connector of the semiconductor die to a conductive feature disposed outside of the semiconductor die.

An embodiment method includes encapsulating a semiconductor die in an encapsulant, planarizing the encapsulant, and depositing a polymer material on the encapsulant. The method further includes planarizing the polymer material and forming a metallization pattern on the polymer material. The metallization pattern electrically connects a die connector of the semiconductor die to a conductive feature disposed outside of the semiconductor die.

A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.

The method of the present invention improves quality and reliability of resin mold-type semiconductor devices. The method includes the steps of placing a lead frame such that cavities of a mold match with device formation regions of the lead frame, respectively, and forming encapsulation bodies that encapsulate semiconductor chips by flowing encapsulating resin into the cavities. The mold with an upper mold half and a lower mold half clamped together has a plurality of first gates that allow the cavities to communicate with a runner, and a dummy-cavity gate that allows a dummy cavity to communicate with the runner. During a resin molding process, from the time when the resin starts flowing into the mold to the time when the encapsulation bodies are formed, an orifice of each cavity gate is larger in size than an orifice of the dummy-cavity gate.

The method of the present invention improves quality and reliability of resin mold-type semiconductor devices. The method includes the steps of placing a lead frame such that cavities of a mold match with device formation regions of the lead frame, respectively, and forming encapsulation bodies that encapsulate semiconductor chips by flowing encapsulating resin into the cavities. The mold with an upper mold half and a lower mold half clamped together has a plurality of first gates that allow the cavities to communicate with a runner, and a dummy-cavity gate that allows a dummy cavity to communicate with the runner. During a resin molding process, from the time when the resin starts flowing into the mold to the time when the encapsulation bodies are formed, an orifice of each cavity gate is larger in size than an orifice of the dummy-cavity gate.