A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2).

A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.

An apparatus includes an integrated circuit and a substrate coupled to the integrated circuit. The substrate includes a primary layer having a first surface that is a first external surface of the substrate. The primary layer includes an open area that extends through the primary layer to an inner layer of the substrate. The substrate includes a secondary layer. The inner layer is located between the primary layer and the secondary layer. The inner layer includes a third surface that is orientated approximately parallel to the first surface of the primary layer. A portion of the third surface of the inner layer is exposed via the open area of the primary layer. A first plurality of wire bond pads are disposed on the portion of the third surface of the inner layer that is exposed via the open area of primary layer.

The present disclosure provides a semiconductor package. The semiconductor package includes a carrier member, a plurality of inductors and a memory chip. The carrier member includes a first surface, a second surface and a centrally-located opening. The carrier member also includes a plurality of conductive pads on the second surface proximal to the opening. The memory chip is attached to the carrier member in a face-down manner. The memory chip includes a plurality of bidirectional and unidirectional signal-transmission pins electrically coupled to the inductors. The memory chip also includes a plurality of bonding pads. A plurality of bonding wires, passing through the opening, electrically connect the bonding pads on the memory chip to the conductive pads on the carrier member. A first insulative structure substantially encapsulates the memory chip and the inductors. A plurality of solder balls are attached to the second surface of the carrier member.

The present disclosure provides a semiconductor package. The semiconductor package includes a carrier member, a plurality of inductors and a memory chip. The carrier member includes a first surface, a second surface and a centrally-located opening. The carrier member also includes a plurality of conductive pads on the second surface proximal to the opening. The memory chip is attached to the carrier member in a face-down manner. The memory chip includes a plurality of bidirectional and unidirectional signal-transmission pins electrically coupled to the inductors. The memory chip also includes a plurality of bonding pads. A plurality of bonding wires, passing through the opening, electrically connect the bonding pads on the memory chip to the conductive pads on the carrier member. A first insulative structure substantially encapsulates the memory chip and the inductors. A plurality of solder balls are attached to the second surface of the carrier member.

There is provided a palladium-coated copper bonding wire that does not cause a shrinkage cavity during first bonding, has high bonding reliability, and is capable of maintaining excellent bonding reliability for a long period of time even in high-temperature and high-humidity environments. A palladium-coated copper bonding wire in which a concentration of palladium is 1.0 mass % or more and 4.0 mass % or less relative to the total of copper, palladium, and a sulfur group element, a total concentration of the sulfur group element is 50 mass ppm or less, and a concentration of sulfur is 5 mass ppm or more and 12 mass ppm or less, a concentration of selenium is 5 mass ppm or more and 20 mass ppm or less, or a concentration of tellurium is 15 mass ppm or more and 50 mass ppm or less, and the palladium-coated copper bonding wire including a palladium-concentrated region with the average concentration of palladium of 6.5 atom % or more and 30.0 atom % or less relative to the total of copper and palladium within a range from a surface of a tip portion of a free air ball formed at a tip of the wire to 5.0 nm or more and 100.0 nm or less.

Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements.

A semiconductor device, a drain electrode terminal supporting the semiconductor device and connected directly to a drain electrode pad, a source electrode terminal connected to a source electrode pad, and a gate electrode terminal are provided, wherein the source electrode terminal includes a wire post, a first lead extending from one end of the wire post, and a second lead extending from another end of the wire post, wherein the source electrode pad and the wire post of the source electrode terminal are connected to each other through a plurality of bonding wires, and wherein the semiconductor device, a surface, supporting the semiconductor device thereon, of the drain electrode terminal, the wire post of the source electrode terminal, the bonding wires, and part of the gate electrode terminal are covered with a mold resin.

A semiconductor device, a drain electrode terminal supporting the semiconductor device and connected directly to a drain electrode pad, a source electrode terminal connected to a source electrode pad, and a gate electrode terminal are provided, wherein the source electrode terminal includes a wire post, a first lead extending from one end of the wire post, and a second lead extending from another end of the wire post, wherein the source electrode pad and the wire post of the source electrode terminal are connected to each other through a plurality of bonding wires, and wherein the semiconductor device, a surface, supporting the semiconductor device thereon, of the drain electrode terminal, the wire post of the source electrode terminal, the bonding wires, and part of the gate electrode terminal are covered with a mold resin.

A bonding wire for connecting a first pad to a second pad is provided. The bonding wire includes a ball part bonded to the first pad, a neck part formed on the ball part, and a wire part extending from the neck part to the second pad. Less than an entire portion of a top surface of the neck part is covered by the wire part, and the wire part is in contact with the neck part, the ball part, and the first pad.