A semiconductor device includes a semiconductor element having a surface electrode layer; a first wire that is electrically connected to the first main surface of the surface electrode layer at a plurality of first connecting portions and is arranged in a first direction on the first main surface; and a second wire that is electrically connected to the first main surface of the surface electrode layer at a second connecting portion and is arranged in a second direction on the first main surface, wherein a second circle equivalent diameter, which is a diameter of a circle having a same cross-sectional area as the second wire, is larger than a first circle equivalent diameter, which is a diameter of a circle having a same cross-sectional area as the first wire.

A power semiconductor device in which the size of an insulating substrate is reduced and connection failure can be suppressed includes an insulating substrate, a semiconductor element, and a printed circuit board. The semiconductor element is bonded to one main surface of the insulating substrate. The printed circuit board is bonded to face the semiconductor element. The semiconductor element has a main electrode and a signal electrode. The printed circuit board includes a core member, a first conductor layer, and a second conductor layer. The second conductor layer has a bonding pad. The printed circuit board has a missing portion. A metal column portion is arranged to pass through the inside of the missing portion and reach the insulating substrate. The signal electrode and the bonding pad are connected by a metal wire. The metal column portion and the insulating substrate are bonded.

A power semiconductor device in which the size of an insulating substrate is reduced and connection failure can be suppressed includes an insulating substrate, a semiconductor element, and a printed circuit board. The semiconductor element is bonded to one main surface of the insulating substrate. The printed circuit board is bonded to face the semiconductor element. The semiconductor element has a main electrode and a signal electrode. The printed circuit board includes a core member, a first conductor layer, and a second conductor layer. The second conductor layer has a bonding pad. The printed circuit board has a missing portion. A metal column portion is arranged to pass through the inside of the missing portion and reach the insulating substrate. The signal electrode and the bonding pad are connected by a metal wire. The metal column portion and the insulating substrate are bonded.

A semiconductor device includes a baseplate and a case which includes an external wall surrounding an internal space and a dividing wall extending in a first direction and separating the space into compartments. The dividing wall has a lower end fixed to the principal surface and includes, on a sidewall, a terrace positioned further away from the principal surface than the lower end and hanging out toward the space compared to the lower end in a second direction parallel to the principal surface and perpendicular to the first direction. A terminal's bonding part, to which a wire is bonded, is disposed on the terrace. A ratio of the wire's diameter to the bonding part's width in the first direction is set to ≤0.15, which prevents a situation where bonding power is not sufficiently applied to the bonding part during ultrasonic bonding of the wire, thus increasing the bonding strength.

A power semiconductor module includes a substrate with a metallization layer and a power semiconductor chip bonded to the metallization layer of the substrate. A metallic plate has a first surface bonded to a surface of the power semiconductor chip opposite to the substrate. The metallic plate has a central part and a border that are both bonded to the power semiconductor chip. The border of the metallic plate is structured in such a way that the metallic plate has less metal material per volume at the border as compared to the central part of the metallic plate. Metallic interconnection elements are bonded to a second surface of the metallic plate at the central part.

Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.

A semiconductor package is provided. The semiconductor package includes: a package substrate; a first semiconductor chip mounted on the package substrate; a second semiconductor chip mounted on the package substrate; an adhesive film provided on an upper surface the first semiconductor chip and an upper surface of the second semiconductor chip; and a third semiconductor chip attached to the first semiconductor chip, the second semiconductor chip by the adhesive film. The first and second semiconductor chips have different heights, and a thickness of the adhesive film at a portion thereof contacting the first semiconductor chip is different from a thickness of the adhesive film at a portion thereof contacting the second semiconductor chip.

An integrated circuit (IC) includes semiconductor substrate with a metal stack including a lower, upper and a top metal layer that includes bond pads and a detection bond pad (DBP). A wirebond damage detector (WDD) includes the DBP over a first and second connected structure. The first and second connected structures both include spaced apart top segments of the upper metal layer coupled to spaced apart bottom segments of the lower metal layer. The DBP is coupled to one end of the first connected structure, and ≥1 metal trace is coupled to another end extending beyond the DBP to a first test pad. The second connected structure includes metal traces coupled to respective ends each extending beyond the DBP to a second test pad and to a third test pad.

An integrated circuit (IC) includes semiconductor substrate with a metal stack including a lower, upper and a top metal layer that includes bond pads and a detection bond pad (DBP). A wirebond damage detector (WDD) includes the DBP over a first and second connected structure. The first and second connected structures both include spaced apart top segments of the upper metal layer coupled to spaced apart bottom segments of the lower metal layer. The DBP is coupled to one end of the first connected structure, and ≥1 metal trace is coupled to another end extending beyond the DBP to a first test pad. The second connected structure includes metal traces coupled to respective ends each extending beyond the DBP to a second test pad and to a third test pad.

A semiconductor package includes a conductive pad, a semiconductor die with an aluminum bond pad over a dielectric layer of the semiconductor die, a gold bump on the aluminum bond pad, a first intermetallic layer of gold and aluminum between the aluminum bond pad and the gold bump, a copper ball bond on the gold bump, a second intermetallic layer of copper and gold between the copper ball bond and the gold bump, a copper wire extending from the copper ball bond to the conductive pad, a stitch bond between the copper wire and the conductive pad.