Patent classifications
H01L2224/85205
Systems and methods for optimizing looping parameters and looping trajectories in the formation of wire loops
A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2).
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
A semiconductor device includes a heat-dissipating base, a first conductive layer bonded to the top surface of the heat-dissipating base, an AlN insulating substrate bonded to the top surface of the first conductive layer, and an electrode terminal having one edge bending to form a bonding edge whose bottom surface faces the top surface of the second conductive layer and is solid-state bonded to a portion of the top surface of the second conductive layer. The crystal grain diameter at the bonded interface of the second conductive layer and electrode terminal is less than or equal to 1 μm, and indentations from the ultrasonic horn are left in the top surface of the bonding edge.
Semiconductor Device Including Bonding Pad Metal Layer Structure
A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.
Semiconductor Device Including Bonding Pad Metal Layer Structure
A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.
Wire bonding method and wire bonding structure
A wire bonding method includes steps of: forming a Free Air Ball (FAB) at an end of a metal wire; pressing the FAB onto a flat surface of a workpiece to deform the FAB; contacting the deformed FAB to a metal pad, wherein the metal pad is made of a first material and the metal wire is made of a second material, and a hardness of the first material is smaller than a hardness of the second material; and bonding the deformed FAB on the metal pad.
Method for calibrating wire clamp device
A method for calibrating a wire clamp device includes: preparing a wire clamp device provided with a pair of arm parts having tips for clamping a wire, the arms extending from the tips toward base ends, and a drive part provided with a piezoelectric element for drive, connected to the base ends of the pair of arm parts and opening/closing the tips of the pair of arm parts; a step of detecting, by electrical continuity between the tips, a timing at which the pair of arm parts enters a closed state when the piezoelectric element for drive is driven, and acquiring a reference voltage; and a step of calibrating, on the basis of the reference voltage, an application voltage to be applied to the piezoelectric element for drive. Thus, it is possible to perform accurate and stable wire bonding.
Wire-bonding apparatus and method of manufacturing semiconductor device
Provided is a wire-bonding apparatus (10) including: a capillary (28) through which a wire (30) inserted; and a controller (80). The controller (80) is configured to execute operations including: a disconnection operation, after the second bonding operation, of moving the capillary through which the wire is inserted within a horizontal plane vertical to an axial direction of the capillary while the wire is held in the clamped state, and thereby disconnecting the wire from the second bonding point; a preliminary bonding operation of feeding the wire from the second bonding point to a predetermined preliminary bonding point, and performing preliminary bonding at the preliminary bonding point; and a shaping operation, after the preliminary bonding operation, of shaping the wire projecting from a tip of the capillary into a predetermined flexed shape.
ROBUST LOW INDUCTANCE POWER MODULE PACKAGE
A method and system for a power module is provided. The power module includes a first substrate including a first conductive substrate having a first plurality of power semiconductor switches arranged thereon, and at least one second conductive substrate electrically coupled to the first conductive substrate. A first terminal is electrically coupled to the first conductive substrate. The power module also includes a second substrate including a third conductive substrate having a second plurality of power semiconductor switches arranged thereon, and at least one fourth conductive substrate electrically coupled to the third conductive substrate. The third conductive substrate is electrically coupled to the second conductive substrate. A second terminal is electrically coupled to the fourth conductive substrate.
ROBUST LOW INDUCTANCE POWER MODULE PACKAGE
A method and system for a power module is provided. The power module includes a first substrate including a first conductive substrate having a first plurality of power semiconductor switches arranged thereon, and at least one second conductive substrate electrically coupled to the first conductive substrate. A first terminal is electrically coupled to the first conductive substrate. The power module also includes a second substrate including a third conductive substrate having a second plurality of power semiconductor switches arranged thereon, and at least one fourth conductive substrate electrically coupled to the third conductive substrate. The third conductive substrate is electrically coupled to the second conductive substrate. A second terminal is electrically coupled to the fourth conductive substrate.
Semiconductor wire bonding machine cleaning device and method
A methodology and medium for regular and predictable cleaning the support hardware such as capillary tube in semiconductor assembly equipment components, while it is still in manual, semi-automated, and automated assembly are disclosed. The cleaning material may include a cleaning pad layer and one or more intermediate layers that have predetermined characteristics.