Cryogenic integrated circuits are provided. A cryogenic integrated circuit includes a thermally conductive base, a data processor, a storage device, a buffer device, a thermally conductive shield and a cooling pipe. The data processor is located on the thermally conductive base. The storage device is located on the thermally conductive base and disposed aside and electrically connected to the data processor. The buffer device is disposed on the data processor. The thermally conductive shield covers the data processor, the storage device and the buffer device. The cooling pipe is located in physical contact with the thermally conductive base and disposed at least corresponding to the data processor.

Cryogenic integrated circuits are provided. A cryogenic integrated circuit includes a thermally conductive base, a data processor, a storage device, a buffer device, a thermally conductive shield and a cooling pipe. The data processor is located on the thermally conductive base. The storage device is located on the thermally conductive base and disposed aside and electrically connected to the data processor. The buffer device is disposed on the data processor. The thermally conductive shield covers the data processor, the storage device and the buffer device. The cooling pipe is located in physical contact with the thermally conductive base and disposed at least corresponding to the data processor.

The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, a top device die and an additional package substrate. The bottom device die is attached on the package substrate. The top device die is attached on the bottom device die with its active side facing away from the bottom device die. A first portion of die I/Os at the active side of the top device die are electrically connected to the package substrate. The additional package substrate is attached on the active side of the top device die, and electrically connected to the package substrate and a second portion of the die I/Os of the top device die.

The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, a top device die and an additional package substrate. The bottom device die is attached on the package substrate. The top device die is attached on the bottom device die with its active side facing away from the bottom device die. A first portion of die I/Os at the active side of the top device die are electrically connected to the package substrate. The additional package substrate is attached on the active side of the top device die, and electrically connected to the package substrate and a second portion of the die I/Os of the top device die.

The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, a top device die and an additional package substrate. The bottom device die is attached on the package substrate. The top device die is attached on the bottom device die with its active side facing away from the bottom device die. A first portion of die I/Os at the active side of the top device die are electrically connected to the package substrate. The additional package substrate is attached on the active side of the top device die, and electrically connected to the package substrate and a second portion of the die I/Os of the top device die.

The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, a top device die and an additional package substrate. The bottom device die is attached on the package substrate. The top device die is attached on the bottom device die with its active side facing away from the bottom device die. A first portion of die I/Os at the active side of the top device die are electrically connected to the package substrate. The additional package substrate is attached on the active side of the top device die, and electrically connected to the package substrate and a second portion of the die I/Os of the top device die.

An image sensor chip-scale package includes a pixel array, a cover glass covering the pixel array, a dam, and an adhesive layer. The pixel array is embedded in a substrate top-surface of a semiconductor substrate. The semiconductor substrate includes a plurality of conductive pads in a peripheral region of the semiconductor substrate surrounding the pixel array. The dam at least partially surrounds the pixel array and is located (i) between the cover glass and the semiconductor substrate, and (ii) on a region of the substrate top-surface between the pixel array and the plurality of conductive pads. The adhesive layer is (i) located between the cover glass and the semiconductor substrate, (ii) at least partially surrounding the dam, and (iii) configured to adhere the cover glass to the semiconductor substrate.

An image sensor chip-scale package includes a pixel array, a cover glass covering the pixel array, a dam, and an adhesive layer. The pixel array is embedded in a substrate top-surface of a semiconductor substrate. The semiconductor substrate includes a plurality of conductive pads in a peripheral region of the semiconductor substrate surrounding the pixel array. The dam at least partially surrounds the pixel array and is located (i) between the cover glass and the semiconductor substrate, and (ii) on a region of the substrate top-surface between the pixel array and the plurality of conductive pads. The adhesive layer is (i) located between the cover glass and the semiconductor substrate, (ii) at least partially surrounding the dam, and (iii) configured to adhere the cover glass to the semiconductor substrate.

Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.

Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.