The present invention relates to an electronic circuit arrangement (10) comprising: a substrate (12) having a first surface (12a) and a second surface (12b), an electronic circuit, an electrical connection part (16) for providing an electrical connection to the electronic circuit and being arranged on the first surface (12a), and at least one electrical wire (18). The electrical wire (18) comprises at least one conductive core (20) and an isolation (22) surrounding the conductive core (20). An end portion (18a) of the electrical wire (18) is an isolation-free portion for allowing access to the conductive core (20), wherein the end portion (18a) of the electrical wire (18) is connected to the electrical connection part (16). At least one through-hole (24) extending from the first surface (12a) to the second surface (12b) is provided in the substrate (12), wherein the electrical wire (18) is arranged through the through-hole (24).

A method includes attaching a micro-coaxial wire to electrical contacts in a substrate, the micro-coaxial wire including a core wire, a bonded section, and a shield layer, the electrical contacts including a first electrical contact and a second electrical contact. Attaching the micro-coaxial wire to the electrical contacts includes connecting a core wire of the micro-coaxial wire to the first electrical contact including forming a bonded section by bonding the core wire to the first electrical contact, and then depositing solder onto the bonded section of the core wire.

The present disclosure relates to a power module including a plurality of semiconductor elements through which a main current flows in a thickness direction; a substrate on which the plurality of semiconductor elements are mounted; a base plate on which the substrate is mounted; a case that is bonded to the base plate and houses the plurality of semiconductor elements; a plurality of main wiring boards incorporated in an upper portion of the case on a side opposite to the base plate and arranged in parallel to the base plate; and a plurality of wires bonded to lower surfaces of the plurality of main wiring boards that face the plurality of semiconductor elements, in which an upper surface electrode of each of the plurality of semiconductor elements is electrically connected to a corresponding one of the plurality of main wiring boards with the plurality of wires and a bonding material.

An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

Electronic assembly methods and structures are described. In an embodiment, an electronic assembly method includes bringing together an electronic component and a routing substrate, and directing a large area photonic soldering light pulse toward the electronic component to bond the electronic component to the routing substrate.

An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

A semiconductor device includes: an interposer mounted on an upper surface of a printed board; a first semiconductor element mounted on an upper surface of the interposer; a second semiconductor element mounted on the upper surface of the printed board and performing conversion between an optical signal and an electrical signal; and a bonding wire connecting a first pad and a second pad, the first pad being provided on the upper surface of the interposer, the second pad being provided on an upper surface of the second semiconductor element, the first semiconductor element lowers a speed of an electrical signal input from the second semiconductor element and outputs the electrical signal to the printed board, and increases a speed of an electrical signal and outputs the electrical signal to the second semiconductor element via the interposer and the bonding wire.

An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.