Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.

A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a first sidewall substantially orthogonal to the first surface and the second surface; an isolation layer surrounding and contacted with the first sidewall of the substrate; a die disposed over the second surface of the substrate; a first conductive bump disposed at the first surface of the substrate; and a second conductive bump disposed between the substrate and the die.

A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a first sidewall substantially orthogonal to the first surface and the second surface; an isolation layer surrounding and contacted with the first sidewall of the substrate; a die disposed over the second surface of the substrate; a first conductive bump disposed at the first surface of the substrate; and a second conductive bump disposed between the substrate and the die.

A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.

A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.

A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.

A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.

A method of forming a package and a package are provided. The method includes placing a main die and a dummy die side by side on a carrier substrate. The method also includes forming a molding material along sidewalls of the main die and the dummy die. The method also includes forming a redistribution layer comprising a plurality of vias and conductive lines over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die. The method also includes removing the carrier substrate.

A method of forming a package and a package are provided. The method includes placing a main die and a dummy die side by side on a carrier substrate. The method also includes forming a molding material along sidewalls of the main die and the dummy die. The method also includes forming a redistribution layer comprising a plurality of vias and conductive lines over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die. The method also includes removing the carrier substrate.

A package structure includes a semiconductor package, a thermal conductive gel, a thermal conductive film and a heat spreader. The thermal conductive gel is disposed over the semiconductor package. The thermal conductive film is disposed over the semiconductor package and the thermal conductive gel. A thermal conductivity of the thermal conductive film is different from a thermal conductivity of the thermal conductive gel. The thermal conductive film is surrounded by the heat spreader.