Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.

A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.

Methods related to radio-frequency (RF) filters on silicon-on-insulator (SOI) substrate. In some embodiments, a method of manufacturing a radio-frequency device can include providing a semiconductor die including a radio-frequency circuit, a first side and a second side, and a plurality of vias, each via configured to provide an electrical connection between the first side and the second side of the semiconductor die. The method can further include mounting a filter device on the first side of the semiconductor die, the filter device in communication with the radio-frequency circuit, the radio-frequency circuit implemented in a layer on the first side of the semiconductor die and at least some of the vias coupled with the radio-frequency circuit to support an electrical connection between the radio-frequency circuit and mounting features on the second side of the semiconductor die.

Methods related to radio-frequency (RF) filters on silicon-on-insulator (SOI) substrate. In some embodiments, a method of manufacturing a radio-frequency device can include providing a semiconductor die including a radio-frequency circuit, a first side and a second side, and a plurality of vias, each via configured to provide an electrical connection between the first side and the second side of the semiconductor die. The method can further include mounting a filter device on the first side of the semiconductor die, the filter device in communication with the radio-frequency circuit, the radio-frequency circuit implemented in a layer on the first side of the semiconductor die and at least some of the vias coupled with the radio-frequency circuit to support an electrical connection between the radio-frequency circuit and mounting features on the second side of the semiconductor die.

An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

Methods related to radio-frequency (RF) filters on silicon-on-insulator (SOI) substrate. In some embodiments, a method of manufacturing a radio-frequency device can include providing a semiconductor die including a radio-frequency circuit, a first side and a second side, and a plurality of vias, each via configured to provide an electrical connection between the first side and the second side of the semiconductor die. The method can further include mounting a filter device on the first side of the semiconductor die, the filter device in communication with the radio-frequency circuit, the radio-frequency circuit implemented in a layer on the first side of the semiconductor die and at least some of the vias coupled with the radio-frequency circuit to support an electrical connection between the radio-frequency circuit and mounting features on the second side of the semiconductor die.

Methods related to radio-frequency (RF) filters on silicon-on-insulator (SOI) substrate. In some embodiments, a method of manufacturing a radio-frequency device can include providing a semiconductor die including a radio-frequency circuit, a first side and a second side, and a plurality of vias, each via configured to provide an electrical connection between the first side and the second side of the semiconductor die. The method can further include mounting a filter device on the first side of the semiconductor die, the filter device in communication with the radio-frequency circuit, the radio-frequency circuit implemented in a layer on the first side of the semiconductor die and at least some of the vias coupled with the radio-frequency circuit to support an electrical connection between the radio-frequency circuit and mounting features on the second side of the semiconductor die.