A semiconductor device includes: circuit devices on a first substrate; a lower interconnection structure electrically connected to the circuit devices; a lower bonding structure connected to the lower interconnection structure; an upper bonding structure on the lower bonding structure; an upper interconnection structure connected to the upper bonding structure; a second substrate on the upper interconnection structure; gate electrodes between the upper interconnection structure and the second substrate; channel structures penetrating the gate electrodes and each including a channel layer; via patterns on the second substrate; a source contact plug spaced apart from the second substrate on an external side of the second substrate and having an upper surface higher than the second substrate and a lower surface lower than a lowermost gate electrode; and a source connection pattern contacting upper surfaces of each of the via patterns and the upper surface of the source contact plug.

The present application discloses a semiconductor chip, a semiconductor device and an electrostatic discharge (ESD) protection method for a semiconductor device. The semiconductor chip includes an electrical contact, an application circuit, and an ESD protection unit. The application circuit performs operations according to a one signal received by the electrical contact. The ESD protection unit is coupled to the electrical contact. The capacitance of the ESD protection unit is adjustable.

Disclosed is a semiconductor package comprising a first chip stack including on a substrate a plurality of first semiconductor chips in an offset stack structure and stacked to expose a connection region at a top surface of each of the first semiconductor chips, a second semiconductor chip on the substrate and horizontally spaced apart from the first chip stack, a spacer on the second semiconductor chip, and a second chip stack including third semiconductor chips in an offset stack structure on the first chip stack and the spacer. Each of the first semiconductor chips includes a first chip pad on the connection region and a first wire that extends between the first chip pad and the substrate. The first wire of an uppermost one of the first semiconductor chips is horizontally spaced apart from a lowermost one of the third semiconductor chips.

A semiconductor package includes; a package substrate including an upper surface with a bonding pad, a lower semiconductor chip disposed on the upper surface of the package substrate, wherein an upper surface of the lower semiconductor chip includes a connect edge region including a connection pad and an open edge region including a dam structure including dummy bumps, a bonding wire having a first height above the upper surface of the lower semiconductor chip and connecting the bonding pad and the connection pad, an upper semiconductor chip disposed on the upper surface of the lower semiconductor chip using an inter-chip bonding layer, and a molding portion on the package substrate and substantially surrounding the lower semiconductor chip and the upper semiconductor chip.

Electronic device package technology is disclosed. In one example, an electronic device comprises a die (18) having a bond pad (22); and a decoupling capacitor (14) mounted on the die (18) and electrically coupled to the die (18). A method for making an electronic device comprises mounting a decoupling capacitor (14) on a die (18); and electrically coupling the decoupling capacitor (14) to the die (18).

An organic interposer includes: a first organic insulating layer including a groove; a first metal wire located in the groove; a barrier metal material covering the first metal wire; and a second metal wire located above the first metal wire, wherein the barrier metal material includes: a first barrier metal film interposed between the first metal wire and an inner surface of the groove; and a second barrier metal film located on the first metal wire, and wherein the second metal wire is in contact with both of the first barrier metal film and the second barrier metal film.

Apparatus and methods are provided for integrated circuit packages having a low z-height. In an example, a method can include mounting a first integrated circuit sub-package to a first package substrate wherein the sub-package substrate spans an opening of the first package substrate, mounting a second integrated circuit package to a second package substrate, and mounting the first package substrate with the second package substrate wherein the mounting includes locating a portion of the second integrated circuit package within the opening of the first package substrate.

A semiconductor package is provided. The semiconductor package includes: a substrate; a first buffer chip and a second buffer chip located on an upper part of the substrate; a plurality of nonvolatile memory chips located on the upper part of the substrate and including a first nonvolatile memory chip and a second nonvolatile memory chip, the first nonvolatile memory chip being electrically connected to the first buffer chip, and the second nonvolatile memory chip being electrically connected to the second buffer chip; a plurality of external connection terminals connected to a lower part of the substrate; and a rewiring pattern located inside the substrate. The rewiring pattern is configured to diverge an external electric signal received through one of the plurality of external connection terminals into first and second signals, transmit the first signal to the first buffer chip, and transmit the second signal to the second buffer chip.

Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.

A semiconductor device includes a first semiconductor chip having a first surface and a second surface; a first adhesive layer on the first surface; a second semiconductor chip that includes a third surface and a fourth surface, and a connection bump on the third surface. The connection bump is coupled to the first adhesive layer. The semiconductor device includes a wiring substrate connected to the connection bump. The semiconductor device includes a first resin layer covering the connection bump between the second semiconductor chip and the wiring substrate, and covers one side surface of the second semiconductor chip connecting the third surface and the fourth surface. The first adhesive layer covers an upper portion of the at least one side surface. The first resin layer covers a lower portion of the t least one side surface. The first adhesive layer and the first resin layer contact each other.