A semiconductor device has a first substrate and a first electrical component disposed over the first substrate. A first support frame is disposed over the first substrate. The first support frame has a horizontal support channel extending across the first substrate and a vertical support brace extending from the horizontal support channel to the first substrate. The first support frame can have a vertical shielding partition extending from the horizontal support channel to the first substrate. An encapsulant is deposited over the first electrical component and first substrate and around the first support frame. A second electrical component is disposed over the first electrical component. A second substrate is disposed over the first support frame. A second electrical component is disposed over the second substrate. A third substrate is disposed over the second substrate. A second support frame is disposed over the second substrate.

A device die including a first semiconductor die, a second semiconductor die, an anti-arcing layer and a first insulating encapsulant is provided. The second semiconductor die is stacked over and electrically connected to the first semiconductor die. The anti-arcing layer is in contact with the second semiconductor die. The first insulating encapsulant is disposed over the first semiconductor die and laterally encapsulates the second semiconductor die. Furthermore, methods for fabricating device dies are provided.

A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D random-access memory (3D-RAM) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-RAM arrays. The first die does not comprise the off-die peripheral-circuit component of the 3D-RAM arrays.

In certain aspects, a semiconductor device includes a substrate, a first trench isolation in the substrate, a second trench isolation in the substrate and surrounding a portion of the substrate, and a first routing electrode layer extending through the first trench isolation. The portion of the substrate is an active region of a transistor.

A semiconductor package includes a semiconductor package includes first, second, third and fourth semiconductor chips sequentially stacked on one another. Each of the first, second, third and fourth semiconductor chips includes a first group of bonding pads and a second group of bonding pads alternately arranged in a first direction and input/output (I/O) circuitry selectively connected to the first group of bonding pads respectively. Each of the first, second and third semiconductor chips includes a first group of through electrodes electrically connected to the first group of bonding pads and a second group of through electrodes electrically connected to the second group of bonding pads.

A package structure includes first/second/third package components, a thermal interface material (TIM) structure overlying the first package component opposite to the second package component, and a heat dissipating component disposed on the third package component and thermally coupled to the first package component through the TIM structure. The first package component includes semiconductor dies and an insulating encapsulation encapsulating the semiconductor dies, the second package component is interposed between the first and third package components, and the semiconductor dies are electrically coupled to the third package component via the second package component. The TIM structure includes a dielectric dam and thermally conductive members including a conductive material, disposed within areas confined by the dielectric dam, and overlying the semiconductor dies. A manufacturing method of a package structure is also provided.

A semiconductor device including a substrate including a cell array region and a connection region, an electrode structure stacked on the substrate, each of the electrodes including a line portion on the cell array region and a pad portion on the connection region, Vertical patterns penetrating the electrode structure, a cell contact on the connection region and connected to the pad portion, an insulating pillar below the cell contact, with the pad portion interposed therebetween may be provided. The pad portion may include a first portion having a top surface higher than the line portion, and a second portion including a first protruding portion, the first protruding portion extending from the first portion toward the substrate and covering a top surface of the insulating pillar.

A method of manufacturing a semiconductor package includes: hybrid-bonding a semiconductor chip, including a through-silicon via, to an upper surface of a semiconductor wafer, wet-etching a surface of the semiconductor chip to expose the through-silicon via, covering the exposed through-silicon via with a material, including an organic resin and an inorganic filler, to form an encapsulation layer, removing an upper surface of the encapsulation layer to expose the through-silicon via, and forming a redistribution structure electrically connected to the through-silicon via.

Provided is a package-on-package (PoP). The PoP includes a lower package, an upper package on the lower package, an interposer substrate disposed between the lower package and the upper package, and a plurality of balls connecting the interposer substrate to the upper package, in which the lower package includes a first substrate, and a first die and a second die disposed side by side in a horizontal direction, on the first substrate, in which the upper package includes a second substrate, a third die on the second substrate, and a plurality of ball pads disposed on a surface of the second substrate, the interposer substrate comprises on a surface thereof a plurality of ball lands to which a plurality of balls are attached, and at least some of the plurality of ball lands overlap the first die and the second die in a vertical direction that intersects the horizontal direction.

A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.