Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first dielectric region and the dielectric layer extending to the die side. A plurality of vias are positioned within the first dielectric region, the vias extending to pads on the die side. Other embodiments are described and claimed.

The package includes: a substrate having at least one circuit layer; at least one electronic component mounted on at least one surface of the substrate; a molded part formed on the surface of the substrate to enclose the electronic component; at least one via formed in the molded part to be electrically connected to the circuit layer of the substrate; and a pattern connected to one end of a plated tail connected to the circuit layer connected to the via and exposed to the exterior of the substrate.

A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

A package includes an interposer, which includes a first substrate free from through-vias therein, redistribution lines over the first substrate, and a first plurality of connectors over and electrically coupled to the redistribution lines. A first die is over and bonded to the first plurality of connectors. The first die includes a second substrate, and through-vias in the second substrate. A second die is over and bonded to the plurality of connectors. The first die and the second die are electrically coupled to each other through the redistribution lines. A second plurality of connectors is over the first die and the second die. The second plurality of connectors is electrically coupled to the first plurality of connectors through the through-vias in the second substrate.

Some embodiments relate to an electronic package. The electronic package includes a substrate that includes a plurality of buildup layers. A first die is embedded in one of the buildup layers on one side of the substrate. A second die is bonded to the substrate within a cavity on an opposing side of the substrate. The first die and the second die may be electrically connected to conductors within the plurality of buildup layers. Other embodiments relate to method of connecting a first die to a second die to form an electronic package. The method includes attaching a first die to a core and fabricating a substrate onto the core. The method further includes creating a cavity in another of the buildup layers on an opposing side of the substrate and attaching a second die to the substrate within the cavity.

An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure.

Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.

In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

A chip package assembly is provided that includes a substrate, at least one integrated circuit (IC) die and a power management integrated circuit (PMIC). In one example, the IC die of the chip package assembly is disposed on a first surface of the substrate. The PMIC die has a first surface having outputs electrically coupled to the second surface of the IC die. The PMIC die also has a second surface facing away from the first surface. The second surface of the PMIC die has inputs that are electrically coupled to the first surface of the substrate.

Several embodiments of microelectronic configurations with logic components and associated methods of manufacturing are disclosed herein. In one embodiment, the configuration includes a substrate with a recess, a first die carried by the substrate wherein the die substantially covers the recess, and a logic component carried by the die in a location exposed by the recess. The logic component can be substantially coplanar with the substrate. The die is electrically connected to a terminal on a one side of the substrate, and the logic component is electrically connected to a terminal on an opposite side of the substrate.