A semiconductor package includes a first package and a second package stacked on the first package. The first package includes a redistribution substrate, a first semiconductor chip on the redistribution substrate, a connection substrate provided on the redistribution substrate to surround the first semiconductor chip as viewed in plan, and an inductor structure provided within a first region of the connection substrate and electrically connected to the first semiconductor chip through the redistribution substrate. The second package includes at least one outer terminal electrically connected to the first package. The outer terminal is provided on a second region of the connection substrate, and when viewed in plan, the first region and the second region are spaced apart from each other.

Some forms relate to a method of making a stretchable computing system. The method includes attaching a first set of conductive traces to a stretchable member; attaching a first electronic component to the first set of conductive traces; adding a first set of flexible conductors to the stretchable member such that the first set of flexible conductors is electrically connected to the first set of conductive traces; adding stretchable material to the stretchable member such that the first set of conductive traces is surrounded by the stretchable member; forming an opening in the stretchable member that exposes the first set of conductive traces; and attaching a second set of conductive traces to the stretchable member such that the second set of conductive traces fills the opening to form a via in the stretchable member that electrically connects the first set of conductive traces with the second set of conductive traces.

A semiconductor package includes a first substrate. A second substrate is spaced apart from the first substrate. A semiconductor chip is between the first substrate and the second substrate. The semiconductor chip is electrically connected to the second substrate. A molding layer surrounds the semiconductor chip. A plate directly contacts a bottom surface of the semiconductor chip. A heat transfer structure connects the plate and the first substrate to each other.

An embedded integrated circuit package is made by providing a substrate with a patterned conductor layer defining bond pads. One or more components typically with upwardly facing contact pads are mounted on the substrate. The contact pads are wire bonded to the bond pads of the patterned conductor layer. A series of layers, each with one or more cut-outs corresponding to locations of the components forms a first solid stack containing cavities accommodating the components and associated wires. In one embodiment the layers are fiberglass layers and the layers are cured in the presence of a resin to form a solid body. In another embodiment the layers are thermoplastic layers.

Some forms relate to a method of making a stretchable computing system. The method includes attaching a first set of conductive traces to a stretchable member; attaching a first electronic component to the first set of conductive traces; adding a first set of flexible conductors to the stretchable member such that the first set of flexible conductors is electrically connected to the first set of conductive traces; adding stretchable material to the stretchable member such that the first set of conductive traces is surrounded by the stretchable member; forming an opening in the stretchable member that exposes the first set of conductive traces; and attaching a second set of conductive traces to the stretchable member such that the second set of conductive traces fills the opening to form a via in the stretchable member that electrically connects the first set of conductive traces with the second set of conductive traces.

Disclosed herein are integrated circuit (IC) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). For example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (RFFE) die in electrical communication with the logic die; and an antenna patch, wherein the RFFE die is closer to the antenna patch than the logic die is to the antenna patch.

Embodiments of inventive concepts disclosed provide a method of manufacturing a semiconductor package. The method includes mounting a plurality of semiconductor chips on a substrate having a connecting member protruding from a top surface of the substrate, applying a non-conductive paste on the substrate and the semiconductor chips, forming a supporting layer coupling each of the semiconductor chips to the substrate, aligning an interposer on the non-conductive paste, forming a non-conductive layer by applying heat while pressing the interposer and the substrate against each other, and cutting the substrate, the non-conductive layer, and the interposer into separate unit packages, each of which include a semiconductor chip.

An electronic structure includes a packaging structure, a circuit pattern structure, an underfill and a protrusion structure. The circuit pattern structure is disposed over the packaging structure. A gap is between the circuit pattern structure and the packaging structure. The underfill is disposed in the gap. The protrusion structure is disposed in the gap, and is configured to facilitate the distributing of the underfill in the gap.

Disclosed herein are integrated circuit (IC) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). For example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (RFFE) die in electrical communication with the logic die; and an antenna patch, wherein the RFFE die is closer to the antenna patch than the logic die is to the antenna patch.

A package structure including a chip stacking structure, a thermal enhance component and a first dielectric material is provided. The thermal enhance component is stacked over and thermally coupled to the chip stacking structure, wherein a first lateral dimension of the thermal enhance component is greater than a second lateral dimension of the chip stacking structure. The first dielectric material laterally encapsulates the thermal enhance component and the chip stacking structure.