A semiconductor package is provided. The semiconductor package includes a first substrate including a first, second and third under-bump patterns; a semiconductor chip provided on the first substrate; conductive structures provided on the first substrate; and a second substrate provided on the semiconductor chip and the conductive structures. The third under-bump pattern is electrically isolated from the first and second under-bump patterns. The conductive structures include: a first conductive structure coupled to the first under-bump pattern; a second conductive structure coupled to the second under-bump pattern; and a third conductive structure coupled to the third under-bump pattern and provided adjacent to the first and second conductive structures. The third conductive structure is provided between the first conductive structure and the second conductive structure, the first under-bump pattern is wider than the third under-bump pattern, and the second under-bump pattern is wider than the third under-bump pattern.

A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an underfill layer. The first semiconductor package includes a plurality of lower semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the lower semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of lower semiconductor chips, wherein the second semiconductor package includes a plurality of upper semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of upper semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of lower semiconductor chips. The underfill layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.

An example microelectronic assembly includes a substrate, a bridge die over the substrate, and a die stack between the substrate and the bridge die, the die stack including a logic die and at least one memory die, where the logic die is between the at least one memory die and the bridge die.

3D semiconductor packages and methods of forming 3D semiconductor package are described herein. The 3D semiconductor packages are formed by mounting a die stack on an interposer, dispensing a thermal interface material (TIM) layer over the die stack and placing a heat spreading element over and attached to the die stack by the TIM layer. The TIM layer provides a reliable adhesion layer and an efficient thermally conductive path between the die stack and interposer to the heat spreading element. As such, delamination of the TIM layer from the heat spreading element is prevented, efficient heat transfer from the die stack to the heat spreading element is provided, and a thermal resistance along thermal paths through the TIM layer between the interposer and heat spreading element are reduced. Thus, the TIM layer reduces overall operating temperatures and increases overall reliability of the 3D semiconductor packages.

A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

A package structure includes a package substrate, a first semiconductor package and a second semiconductor package, an underfill material, a gap filling structure and a heat dissipation structure. The first semiconductor package and the second semiconductor package are electrically bonded to the package substrate. The underfill material is disposed to fill a first space between the first semiconductor package and the package substrate and a second space between the second semiconductor package and the package substrate. The gap filling structure is disposed over the package substrate and in a first gap laterally between the first semiconductor package and the second semiconductor package. The heat dissipation structure is disposed on the package substrate and attached to the first semiconductor package and the second semiconductor package through a thermal conductive layer.

Provided is a semiconductor mounting structure capable of suppressing cracks generated in solder and effectively radiating heat of a heat-generated semiconductor. A DRAM package, a SoC board on which the DRAM package is mounted, and a main board on which the SoC board is mounted are provided. A silicon chip is mounted on a surface of the SoC board facing the main board, and the main board has an opening portion at least at a position facing the silicon chip of the SoC board.

A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, an interposer on the lower semiconductor chip, the interposer including a plurality of pieces spaced apart from each other, an upper semiconductor chip on the interposer, and a molding member covering the lower semiconductor chip and the interposer.