A semiconductor device includes a first semiconductor body including a substrate having a first thickness, wherein the first semiconductor body includes a first active zone that generates or receives radiation, and a second semiconductor body having a second thickness smaller than the first thickness and including a tear-off point is arranged on the substrate and connected in an electrically conducting manner to the first semiconductor body, wherein the second semiconductor body includes a second active zone that generates or receives radiation, and the second active zone generates radiation and the first active zone detects the radiation, and the first semiconductor body includes contacts on its underside for connection to the semiconductor device.

An array substrate for an X-ray detector and an X-ray detector including the reduces or minimizes a leakage current caused by etching of a PIN layer, and also reduces or minimizes light reaction of the PIN layer within a non-pixel region. The array substrate for the X-ray detector includes an integrated PIN layer formed to cover all pixel regions. Upper electrodes, which are spaced apart from each other according to individual pixel regions, are disposed over the PIN layer. A light shielding portion is disposed between neighboring upper electrodes.

A multi-clip structure includes a first clip for die bonding and a second clip for die bonding. The multi-clip structure further includes a retaining tape fixed to the first clip and to the second clip to hold the first clip and the second clip together.

A switched-mode power converter configured to control at least one phase of a polyphase electrical receiver with at least three phases, comprising at least one block of two converter arms, wherein a half-arm of a converter arm comprises: a first set of P2 switches in series; a second set of P2 switches in series; and a third set of diodes, arranged between the first set and the second set, comprising M2 subsets in series, indexed i[[1; M]], respectively comprising N.sub.i2 diodes in parallel.

An array substrate for an X-ray detector and an X-ray detector including the reduces or minimizes a leakage current caused by etching of a PIN layer, and also reduces or minimizes light reaction of the PIN layer within a non-pixel region. The array substrate for the X-ray detector includes an integrated PIN layer formed to cover all pixel regions. Upper electrodes, which are spaced apart from each other according to individual pixel regions, are disposed over the PIN layer. A light shielding portion is disposed between neighboring upper electrodes.

A component carrier has an interconnected stack with at least one electrically insulating layer structure and/or at least one electrically conductive layer structure, a component embedded in the stack and a diode, and at least one heat removal layer configured for removing heat from the diode and substantially fully covering a whole main surface of the component carrier.

A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.

A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.

A semiconductor device includes a semiconductor chip including an upper electrode, a lead frame having a bonding part and a rising part, and a bonding member joining the upper electrode to the bonding part. The upper electrode has electrode lateral surfaces including a first lateral surface. The bonding part has a bonding front surface and terminal lateral surfaces that include a second lateral surface. The bonding part is joined to the upper electrode such that the second lateral surface faces the first lateral surface. The rising part extends upward from the first lateral surface. In a direction parallel to the electrode front surface, a first shortest distance between a center of the electrode front surface in a plan view and the second lateral surface is equal to or greater than 40% of a second shortest distance between the first lateral surface and the second lateral surface.