A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.

A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.

A power semiconductor module including a positive-side switching device and a positive-side diode device which are mounted on a positive-side conductive pattern, and a negative-side switching device and a negative-side diode device which are mounted on an output-side conductive pattern. When an insulating substrate is viewed in plan view, the positive-side diode device and the negative-side diode device are disposed between the positive-side switching device and the negative-side switching device, and the negative-side diode device is disposed closer to the positive-side switching device than the positive-side diode device is.

A wireless communication device that has a circuit board, an RF signal module, a capacitive touch-sensing component, or a functional component, and an antenna component is provided. The touch-sensing signal module is disposed on the circuit board. The capacitive touch-sensing component includes a sensing layer and a ground layer. The sensing layer is electrically connected to the touch-sensing signal module. The antenna component includes a feed point and a radiating body. The feed point is disposed on the ground layer and is electrically connected to the RF single module. The radiating body incorporates at least parts of the ground layer. Alternatively, the feed point is disposed on the sensing layer, and the radiating body incorporates at least parts of the sensing layer. Therefore, the radiating body is incorporated into the sensing layer or ground layer of the capacitive touch-sensing component and can save accommodating space.

Disclosed are systems, devices and methods for providing electrostatic discharge (ESD) protection for integrated circuits. In some implementations, first and second conductors with ohmic contacts on an intrinsic semiconductor region can function similar to an x-i-y type diode, where each of x and y can be n-type or p-type. Such a diode can be configured to turn on under selected conditions such as an ESD event. Such a structure can be configured so as to provide an effective ESD protection while providing little or substantially nil effect on radio-frequency (RF) operating properties of a device.

A switched-mode power converter configured to control at least one phase of a polyphase electrical receiver with at least three phases, comprising at least one block of two converter arms, wherein a half-arm of a converter arm comprises: a first set of P?2 switches in series; a second set of P?2 switches in series; and a third set of diodes, arranged between the first set and the second set, comprising M?2 subsets in series, indexed i?[[1; M]], respectively comprising N.sub.i?2 diodes in parallel.

A semiconductor device includes first and second conductive parts, a first bonding wire connecting the first and second conductive parts and having a non-flat portion between opposite ends thereof so that a portion between the opposite ends is away from the first and second conductive parts, a case having a housing space to accommodate the first and second conductive parts, including a sidewall having first to fourth lateral faces surrounding the housing space to form a rectangular shape in a plan view, and a cover disposed on the sidewall, a sealing member filling the case to seal the first bonding wire, and a first stress relaxer for relieving a stress in the first bonding wire. The first bonding wire extends from the second lateral face toward the fourth lateral face, and the first stress relaxer is positioned between the first bonding wire and the first lateral face.

A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.

A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.

A component carrier has an interconnected stack with at least one electrically insulating layer structure and/or at least one electrically conductive layer structure, a component embedded in the stack and a diode, and at least one heat removal layer configured for removing heat from the diode and substantially fully covering a whole main surface of the component carrier.