A light emitting device including a contact layer, a blocking layer over the contact layer, a protection layer adjacent the blocking layer, a light emitter over the blocking layer, and an electrode layer coupled to the light emitter. The electrode layer overlaps the blocking layer and protection layer, and the blocking layer has an electrical conductivity that substantially blocks flow of current from the light emitter in a direction towards the contact layer. In addition, the protection layer may be conductive to allow current to flow to the light emitter or non-conductive to block current from flowing from the light emitter towards the contact layer.

A light emitting device including a contact layer, a blocking layer over the contact layer, a protection layer adjacent the blocking layer, a light emitter over the blocking layer, and an electrode layer coupled to the light emitter. The electrode layer overlaps the blocking layer and protection layer, and the blocking layer has an electrical conductivity that substantially blocks flow of current from the light emitter in a direction towards the contact layer. In addition, the protection layer may be conductive to allow current to flow to the light emitter or non-conductive to block current from flowing from the light emitter towards the contact layer.

A switching device 1 includes a SiC semiconductor chip 11 which has a gate pad 14, a source pad 13 and a drain pad 12 and in which on-off control is performed between the source and the drain by applying a drive voltage between the gate and the source in a state where a potential difference is applied between the source and the drain, a sense source terminal 4 electrically connected to the source pad 13 for applying the drive voltage, and an external resistance (source wire 16) that is interposed in a current path between the sense source terminal 4 and the source pad 13, is separated from sense source terminal 4, and has a predetermined size.

A semiconductor device, the device including: a first substrate; a first metal layer disposed over the substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 100 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where a typical thickness of the fourth metal layer is at least 50% greater than a typical thickness of the third metal.

A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said second transistors comprises a gate all around structure, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

A semiconductor device capable of securing an insulation distance between a semiconductor element and a wiring. The semiconductor device includes a first semiconductor element, a second semiconductor element, a first wiring, and a second wiring. The first semiconductor element includes a first main surface and a second main surface. An electrode is formed on the first main surface. The second semiconductor element is disposed at a position different from a position of the first semiconductor element in a thickness direction. The first wiring includes an end connected to the electrode. The end includes an upper surface and a cut surface. Diameter of the second wiring is smaller than diameter of the first wiring. The second wiring includes a first end and a second end. The first end is directly connected to the upper surface of the end of the first wiring.

A switching device 1 includes a SiC semiconductor chip 11 which has a gate pad 14, a source pad 13 and a drain pad 12 and in which on-off control is performed between the source and the drain by applying a drive voltage between the gate and the source in a state where a potential difference is applied between the source and the drain, a sense source terminal 4 electrically connected to the source pad 13 for applying the drive voltage, and an external resistance (source wire 16) that is interposed in a current path between the sense source terminal 4 and the source pad 13, is separated from sense source terminal 4, and has a predetermined size.

A 3D semiconductor device, the device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where at least one of the transistors includes a four sided gate.

A semiconductor includes: a substrate; a circuit pattern on the substrate, and including a first region, a second region located away from the first region, and a third region between the first region and the second region; a first chip disposed in the second region and including a diode; a second chip disposed in the third region, the second chip including a vertical transistor having a source pad disposed on a surface opposite to a surface facing the third region in a thickness direction of the substrate, and a gate pad disposed at a position different from the source pad; a first wire including a first bonded portion bonded to the first region, a second bonded portion bonded to the second chip, and a third bonded portion bonded to the first chip; and a second wire arranged to be adjacent to the first wire with the gate pad sandwiched therebetween.

Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.