A method of manufacturing an augmented LED array assembly is described which comprises providing an LED array assembly configured for inclusion in an LED lighting circuit, the LED array assembly comprising a micro-LED array mounted onto a driver integrated circuit, the driver integrated circuit comprising contact pads configured for electrical connections to a circuit board assembly; providing an essentially planar carrier comprising a plurality of contact bridges, each contact bridge extending between a first contact pad and a second contact pad; and mounting the contact bridge carrier to the LED array assembly by forming solder bonds between the first contact pads of the contact bridge carrier and the contact pads of the driver integrated circuit.

A semiconductor package includes: a semiconductor device; a lead frame; a built-in package including an insulated driver having a multi-chip configuration and driving the semiconductor device; a wire connecting the built-in package to the semiconductor device; and a resin sealing the semiconductor device, the lead frame, the built-in package, and the wire, wherein the built-in package is directly joined to the lead frame.

Disclosed are semiconductor packages and thermal management methods thereof. The semiconductor package includes an upper semiconductor chip; and a lower semiconductor chip connected via a plurality of through electrodes to the upper semiconductor chip. The lower semiconductor chip may include at least one temperature sensor configured to sense a temperature of the upper semiconductor chip, a power control unit connected to the at least one temperature sensor, a power switching element connected to at least a first one of the plurality of through electrodes, and a clock control element connected to at least a second one of the plurality of through electrodes.

A method for manufacturing a semiconductor device provided with a semiconductor chip includes: disposing the semiconductor chip such that an electrode of the semiconductor chip is abutted against a peeling portion provided on a substrate; forming an anchor portion, which defines a position of the semiconductor chip and has flexibility so as to be freely bendable, such that the anchor portion covers the peeling portion and the semiconductor chip; forming a sealing portion that is abutted against the anchor portion and has flexibility so as to be freely bendable; and separating the peeling portion and the substrate from the semiconductor chip and the anchor portion and exposing the electrode of the semiconductor chip. The anchor portion is formed by at least one of a vapor phase deposition method, a spray coating method, and an inkjet method.

Disclosed herein are a light source for a display system and methods of fabricating the light source. The light source includes a backplane wafer including a first bonding layer that includes an array of pixel contact pads in a first dielectric layer; a second bonding layer including an array of small metal contact pads in a second dielectric layer; and an array of mesa structures on the second bonding layer and configured to emit light. The second dielectric layer is bonded to the first dielectric layer such that each pixel contact pad of the array of pixel contact pads is in contact with two or more small metal contact pads that are electrically coupled to a same mesa structure of the array of mesa structures.

A display device has a display region and a side region adjacent to the display region. The display device includes a plurality of display units, a plurality of sensing units, a display driver and a sensor driving unit. The plurality of display units are disposed on a first substrate. The plurality of sensing units correspond to the plurality of display units. The plurality of display units and the plurality of sensing units are disposed in the display region. The display driver is coupled to at least a portion of the plurality of display units, and includes a plurality of first transistors. The sensor driving unit is coupled to at least a portion of the plurality of sensing units, and includes at least one second transistor. The plurality of first transistors is disposed in the side region and the at least one second transistor is disposed in the display region.

A semiconductor device includes: a metal sheet; an insulating pattern provided on the metal sheet; a power circuit pattern and a signal circuit pattern that are provided on the insulating pattern; a power semiconductor chip mounted on the power circuit pattern; and a control semiconductor chip that is mounted on the signal circuit pattern and controls the power semiconductor chip. The power semiconductor chip is bonded to the power circuit pattern with a first die bonding material comprised of copper, and the control semiconductor chip is bonded to the signal circuit pattern with a second die bonding material.

Disclosed are a driving backplane and a display apparatus, including: a base substrate, a first conducting layer disposed on one side of the base substrate, a second conducting layer disposed on one side, facing away from the base substrate, of the first conducting layer, and a first insulating layer disposed between the first conducting layer and the second conducting layer, where the second conducting layer includes a plurality of pads, and each pad is connected with the first conducting layer through at least two first via holes.

An LED array assembly may include a hybridized device and a flexible PCB. The hybridized device may include a micro-LED array mounted on a driver IC. The driver IC may include driver IC contact pads on a top surface of the driver IC. The flexible PCB may have a bottom surface, first contact pads on the bottom surface, second contact pads on the bottom surface, and contact bridges. Each of the contact bridges extends from one of the first contact pads to one of the second contact pads. Each of the driver IC contact pads is bonded to a corresponding one of the first contact pads of the flexible PCB.

An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.