An adhesive layer is formed on a semiconductor wafer. The semiconductor wafer is diced to form a plurality of chips. Each of the chips has an adhesive sheet diced from the adhesive layer. Adhesive sheets of the chips are adhered to a carrier. The chips and the carrier are encapsulated by a mold layer. The mold layer is grinded to form a grinded surface. An interconnection structure is formed on the grinded surface. A plurality of semiconductor packages are formed by sawing the mold layer and at least a polyimide layer of the interconnection structure.

A power tube connection structure includes a substrate, a printed circuit board, and a power tube, where a through groove allowing the power tube to pass through is cut into the printed circuit board, a mounting groove is cut into the upper surface of the substrate at a location corresponding to the through groove, one end of the power tube extends through the through groove, and is welded onto a bottom face of the mounting groove, the end of the power tube that extends into the mounting groove abuts onto a side wall of the mounting groove close to an output end of the power amplifier, and a solder flux escape channel is made into the side wall of the mounting groove close to the output end of the power amplifier.

An embedded silicon substrate fan-out type packaging structure comprises: a silicon substrate having a first surface and a second surface opposite thereto, at least one groove extending towards the second surface being formed on the first surface; at least one chip placed in the groove, a pad surface of the chip being opposite to a bottom of the groove; a second dielectric layer formed on the chip and the first surface; at least one layer of metal wiring connected to pads of the chip, formed on the second dielectric layer; under bump metal layers for planting solder balls, formed on an outermost layer of metal wiring; and solder balls or bumps planted on the under bump metal layers, wherein at least one solder ball or bump and at least one under bump metal layer corresponding thereto are on the first surface of the silicon substrate.

The present disclosure provides semiconductor packages and methods for fabricating PoP semiconductor packages. The PoP semiconductor package may comprise a first semiconductor package, the first semiconductor package comprising an anodized metal lid structure comprising (i) a central cavity having a central cavity opening direction and (ii) at least one perimeter cavity having a perimeter cavity opening direction facing in an opposite direction of the central cavity opening direction, a first semiconductor device arranged in the central cavity of the anodized metal lid structure, a redistribution layer electrically coupled to the first semiconductor device, wherein a conductive trace formed in the redistribution layer is exposed to the at least one perimeter cavity, and solder material arranged in the at least one perimeter cavity, and a second semiconductor package, the second semiconductor package comprising at least one conductive post, wherein the at least one conductive post is electrically coupled to the solder material arranged in the at least one perimeter cavity.

Light emitting devices and methods for their manufacture are provided. According to one aspect, a light emitting device is provided that comprises a substrate having a recess, and an interlayer dielectric layer located on the substrate. The interlayer dielectric layer may have a first hole and a second hole, the first hole opening over the recess of the substrate. The light emitting device may further include first and second micro LEDs, the first micro LED having a thickness greater than the second micro LED. The first micro LED and the second micro LED may be placed in the first hole and the second hole, respectively.

Light emitting devices and methods for their manufacture are provided. According to one aspect, a light emitting device is provided that comprises a substrate having a recess, and an interlayer dielectric layer located on the substrate. The interlayer dielectric layer may have a first hole and a second hole, the first hole opening over the recess of the substrate. The light emitting device may further include first and second micro LEDs, the first micro LED having a thickness greater than the second micro LED. The first micro LED and the second micro LED may be placed in the first hole and the second hole, respectively.