Terahertz device A1 includes first resin layer 21, columnar conductor 31, wiring layer 32, terahertz element 11, second resin layer 22, and external electrode 40. Resin layer 21 includes first resin layer obverse face 211 and first resin layer reverse face 212. Columnar conductor 31 includes first conductor obverse face 311 and first conductor reverse face 312, penetrating first resin layer 21 in z-direction. Wiring layer 32 spans between first resin layer obverse face 221 and first conductor obverse face 311. Terahertz element 11 includes element obverse face 111 and element reverse face 112, and converts between terahertz wave and electric energy. Second resin layer 22 includes second resin layer obverse face 221 and second resin layer reverse face 222, and covers wiring layer 32 and terahertz element 11. External electrode 40, disposed offset in a direction first resin layer reverse face 222 faces with respect to first resin layer 32, is electrically connected to columnar conductor 31. Terahertz element 11 is conductively bonded to wiring layer 32.

Various embodiments may provide a semiconductor package. The semiconductor package may include a substrate including a via hole. The semiconductor package may also include a chip attached to the substrate. The semiconductor package may further include a prefabricated ferromagnetic pin having a first portion held by the via hole, a second portion extending from a first end of the first portion, and a third portion extending from a second end of the first portion opposite the first end. The semiconductor package may also include a first magnetic shield structure attached to or extended from the second portion of the prefabricated ferromagnetic pin. The semiconductor package may further include a second magnetic shield structure attached to or extended from the third portion of the prefabricated ferromagnetic pin, such that at least a portion of the chip is between the first magnetic shield structure and the second magnetic shield structure.

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.

The present technology relates to a solid-state imaging unit that makes it possible to increase the number of terminals, a method of producing the same, and an electronic apparatus. A solid-state imaging unit includes: an image sensor substrate including a light receiving region in which pixels that each convert incoming light to an electric signal are arranged in a matrix; a solder ball; a glass substrate opposite the image sensor substrate and the solder ball; and a through electrode that couples a wiring line pattern and the solder ball to each other by penetrating a glass adhesive resin interposed between the wiring line pattern and the solder ball. The solder ball is disposed outside the image sensor substrate in a plane direction. The wiring line pattern being formed on the glass substrate. The present disclosure is applicable, for example, to a package and the like including the image sensor substrate.

A wiring design method and a wiring structure for a package substrate in a flip chip, and a flip chip. The wiring design method includes: arranging bump pads in an array of rows and columns, wherein the bump pads are configured to bond with conductive bumps on a flip chip die, and the bump pads comprise signal pads and non-signal pads; providing the non-signal pad with a via hole; and using a layer of wiring to lead a subset of the signal pads out of an orthographic projection region of the flip chip die on the package substrate, wherein the subset of the signal pads is configured to carry all functional signals required by design specifications of the flip chip die for the array of the bump pads.

A package substrate is adapted to a ball grid array package. The substrate includes two substrate contacts, two solder ball pads, two via holes and two signal lines. A connection line of the two substrate contacts is substantially perpendicular to a connection line of the two solder ball pads. The two substrate contacts are respectively connected to the two via holes by the two signal lines. Each signal line includes a circuit trace section, an approaching section and a bifurcating section connected in sequence. The two circuit trace sections of each signal line are substantially arranged in parallel. The two approaching sections are substantially arranged in parallel and substantially symmetrical about the connection line of the solder ball pads. The two bifurcating sections are substantially symmetrical about the pad connection line and respectively electrically connected to the two via holes.

The invention relates to a component with a main part and a contact structure. The main part has an active zone which is designed to generate electromagnetic radiation at least in some regions during the operation of the component. The contact structure has a plurality of individually actuatable segments. The component has a connection surface and a lateral surface running transversely to the connection surface, and the lateral surface is designed as a radiation passage surface of the component. The connection surface is designed to be structured, wherein the connection surface is defined by common internal boundary surfaces between the main part and the contact structure, and each segment has a local common boundary surface with the main part and is designed for a pixelated current impression into the main part. The invention additionally relates to a method for operating such a component.

A semiconductor device includes a lead frame having a first principal surface which includes a recess, and a second principal surface opposite to the first principal surface, a relay board, disposed in the recess, and having a third principal surface, and a fourth principal surface opposite to the third principal surface, wherein the fourth principal surface opposes a bottom surface of the recess, a first semiconductor chip disposed on the third principal surface, a first conductive material connecting the lead frame and the relay board, and a second conductive material connecting the relay board and the first semiconductor chip. A distance between the second principal surface and the third principal surface is less than or equal to a distance between the second principal surface and the first principal surface.

Terahertz device includes first resin layer, columnar conductor, wiring layer, terahertz element, second resin layer, and external electrode. Resin layer includes first resin layer obverse face and first resin layer reverse face. Columnar conductor includes first conductor obverse face and first conductor reverse face, penetrating first resin layer in z-direction. Wiring layer spans between first resin layer obverse face and first conductor obverse face. Terahertz element includes element obverse face and element reverse face, and converts between terahertz wave and electric energy. Second resin layer includes second resin layer obverse face and second resin layer reverse face, and covers wiring layer and terahertz element. External electrode, disposed offset in a direction first resin layer reverse face faces with respect to first resin layer, is electrically connected to columnar conductor. Terahertz element is conductively bonded to wiring layer.