Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

Integrated circuit (IC) assemblies with stacked compute logic and memory dies, and associated systems and methods, are disclosed. One example IC assembly includes a compute logic die and a stack of memory dies provided above and coupled to the compute logic die, where one or more of the memory dies closest to the compute logic die include memory cells with transistors that are thin-film transistors (TFTs), while one or more of the memory dies further away from the compute logic die include memory cells with non-TFT transistors. Another example IC assembly includes a similar stack of compute logic die and memory dies where one or more of the memory dies closest to the compute logic die include static random-access memory (SRAM) cells, while one or more of the memory dies further away from the compute logic die include memory cells of other memory types.

A package that includes a substrate, a first integrated device coupled to the substrate, a first block device coupled to the substrate, a second encapsulation layer encapsulating the first integrated device and the first block device. The first block device includes a first electrical component, a second electrical component, a first encapsulation layer at least partially encapsulating the first electrical component and the second electrical component, and a first metal layer coupled to the first encapsulation layer.

Integrated circuit (IC) structures include transistor devices with interconnect structures, e.g., a source contact, drain contact, and/or gate contact. The interconnect structures have rounded top surfaces. Contouring the top surfaces of transistor contacts may decrease the likelihood of electrical shorting and may permit a larger volume of insulating dielectric between adjacent contacts.

A die dipping structure includes a plate including a first recessed portion having a first depth and filled with a first flux material. The plate further includes a second recessed portion, isolated from the first recessed portion, with a second depth and filled with a second flux material. The second depth is different from the first depth. The die dipping structure further includes a motor configured to move the plate so as to simultaneously dip a first die and a second die into the flux of the first recessed portion and the flux of the second recessed portion, respectively.

A method includes forming an interconnect component including a plurality of dielectric layers that include an organic dielectric material, and a plurality of redistribution lines extending into the plurality of dielectric layers. The method further includes bonding a first package component and a second package component to the interconnect component, encapsulating the first package component and the second package component in an encapsulant, and precutting the interconnect component using a blade to form a trench. The trench penetrates through the interconnect component, and partially extends into the encapsulant. The method further includes performing a singulation process to separate the first package component and the second package component into a first package and a second package, respectively.

One or more die stacks are disposed on a redistribution layer (RDL) to make an electronic package. The die stacks include a die and one or more Through Silicon Via (TSV) dies. Other components and/or layers, e.g. interposes layers, can be included in the structure. An epoxy layer disposed on the RDL top surface and surrounds and attached to all the TSV die sides and all the die sides. Testing circuitry is located in various locations in some embodiments. Locations including in the handler, die, TSV dies, interposes, etc. Testing methods are disclosed, Methods of making including “die first” and “die last” methods are also disclosed. Methods of making heterogenous integrated structure and the resulting structures are also disclosed, particularly for large scale, e.g. wafer and panel size, applications.

The present disclosure provides a package device and a manufacturing method thereof. The package device includes an electronic device, a conductive pad having a first bottom surface, and a redistribution layer disposed between the conductive pad and the electronic device. The redistribution layer has a second bottom surface, and the conductive pad is electrically connected to the electronic device through the redistribution layer. The first bottom surface is closer to the electronic device than the second bottom in a normal direction of the electronic device.