An electronic device comprises a supporting substrate, a flexible substrate disposed on the supporting substrate, a plurality of electronic units and a conductive pattern layer. The flexible substrate is bent from a front side to a back side of the supporting substrate, and a portion of the flexible substrate is disposed on the back side of the supporting substrate. The electronic units are disposed within a display region of the flexible substrate. The conductive pattern layer extends from the display region to the portion of the flexible substrate, and the conductive pattern layer electrically connects at least two of the electronic units.

Embodiments disclosed herein include electronic packages with improved differential signaling architectures. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises alternating metal layers and dielectric layers. In an embodiment, a first trace is embedded in the package substrate, where the first trace has a first thickness that extends from a first metal layer to a second metal layer. In an embodiment, the electronic package further comprises a first ground plane laterally adjacent to a first side of the first trace, and a second ground plane laterally adjacent to a second side of the first trace.

Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.

Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.

Disclosed are redistribution substrates and semiconductor packages including the same. For example, a redistribution substrate including a dielectric pattern, and a first redistribution pattern in the dielectric pattern is provided. The first redistribution pattern may include: a first via part having a first via seed pattern and a first via conductive pattern on the first via seed pattern, and a first wiring part having a first wiring seed pattern and a first wiring conductive pattern, the first wiring part being disposed on the first via part and having a horizontal width that is different from a horizontal width of the first via part. Additionally, the first wiring seed pattern may cover a bottom surface and a sidewall surface of the first wiring conductive pattern, and the first via conductive pattern is directly connected to the first wiring conductive pattern.

A system including a machine learning processing device and a memory device with microbumps is disclosed. A machine learning processing device is for performing a machine learning operation, where the machine learning processing device includes a first set of microbumps. A memory device is for storing data for the machine learning operation, where the memory device includes a second set of microbumps. The first set of microbumps of the memory device are coupled with the second set of microbumps of the machine learning processing device. The first set of microbumps of the memory device and the second set of microbumps of the machine learning processing device are to transmit the data for the machine learning operation.

A semiconductor package may include a base, a first chip on the base, and first connection patterns that connect and couple the base and the first chip. The first chip may include a substrate, pad patterns on the substrate, a passivation layer on the substrate and having openings, and pillars on the substrate, the pad patterns include a first signal pad and a second signal pad, the first connection patterns are in contact with the pillars, the pillars include a first signal pillar in contact with the first signal pad and a second signal pillar in contact with the second signal pad, the openings in the passivation layer include a first opening having a sidewall facing a side surface of the first signal pillar and surrounding the side surface of the first signal pillar, and a second opening having a sidewall facing a side surface of the second signal pillar and surrounding the side surface of the second signal pillar, and a maximum width of the second opening is greater than a maximum width of the first opening.

A technique capable of shortening process time for plasma cleaning is provided. A method of manufacturing a semiconductor device includes a step of preparing a substrate including a plurality of device regions each including a semiconductor chip electrically connected to a plurality of terminals formed on a main surface by a wire, a step of delivering the substrate while emitting plasma generated in atmospheric pressure to the main surface of the substrate, a step of delivering the substrate while capturing an image of a region of the main surface of the substrate and a step of forming a sealing body by sealing the semiconductor chip and the wire with a resin.

A technique capable of shortening process time for plasma cleaning is provided. A method of manufacturing a semiconductor device includes a step of preparing a substrate including a plurality of device regions each including a semiconductor chip electrically connected to a plurality of terminals formed on a main surface by a wire, a step of delivering the substrate while emitting plasma generated in atmospheric pressure to the main surface of the substrate, a step of delivering the substrate while capturing an image of a region of the main surface of the substrate and a step of forming a sealing body by sealing the semiconductor chip and the wire with a resin.

A semiconductor storage device according to an embodiment includes a substrate, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip includes a first surface contacting with the substrate, a second surface on an opposite side to the first surface, and a first pad provided on the second surface. The second semiconductor chip includes a third surface contacting with the second surface, a fourth surface on an opposite side to the third surface, and a cutout portion. The cutout portion is provided at a corner portion where the third surface crosses a lateral surface between the third surface and the fourth surface. The cutout portion overlaps with at least a part of the first pad as viewed from above the fourth surface.