This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.

Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer.

Some embodiments relate to a semiconductor module having an integrated antenna structure. The semiconductor module has an excitable element and a first ground plane disposed between a substrate and the excitable element. A second ground plane is separated from the first ground plane by the substrate. The second ground plane is coupled to the first ground plane by one or more through-substrate vias (TSVs) that extend through the substrate.

An electronic device includes a substrate including an upper surface, a clock output pad formed in a control device mounting area of the upper surface, a command/address output pad formed in the control device mounting area, a clock signal main wiring connected to the clock output pad, a command/address signal main wiring connected to the command/address output pad, a first clock signal branch wiring branched from the clock signal main wiring at a first branch point of the clock signal main wiring, and a second clock signal branch wiring branched from the clock signal main wiring at a second branch point of the clock signal main wiring, which is located at a downstream side of the clock signal main wiring than the first branch point of the clock signal main wiring.

Embodiments of an embedded mm-wave radio integrated circuit into a substrate of a phased array module are disclosed. In some embodiments, the phased array module includes a first set of substrate layers made of a first material. The mm-wave radio integrated circuit may be embedded in the first set of substrate layers. A second set of substrate layers may be coupled to the first set of substrate layers. The second set of substrate layers may be made of a second material that has a lower electrical loss than the first material. The second set of substrate layers may include a plurality of antenna elements coupled through vias to the mm-wave radio integrated circuit.

Semiconductor packages may include a molded interposer and semiconductor dice mounted on the molded interposer. The molded interposer may include two redistribution layer structures on opposite sides of a molding compound. Electrically conductive vias may connect the RDL structures through the molding compound, and passive devices may be embedded in the molding compound and electrically connected to one of the RDL structures. Each of the semiconductor dice may be electrically connected to, and have a footprint covering, a corresponding one of the passive devices to form a face-to-face connection between each of the semiconductor dice and the corresponding one of the passive devices.

A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts.

A semiconductor package includes an insulating layer including a first face and a second face opposite each other, a redistribution pattern including a wiring region and a via region in the insulating layer, the wiring region being on the via region, and a first semiconductor chip connected to the redistribution pattern. The first semiconductor chip may be on the redistribution pattern. An upper face of the wiring region may be coplanar with the first face of the insulating layer.

A semiconductor package includes an insulating layer including a first face and a second face opposite each other, a redistribution pattern including a wiring region and a via region in the insulating layer, the wiring region being on the via region, and a first semiconductor chip connected to the redistribution pattern. The first semiconductor chip may be on the redistribution pattern. An upper face of the wiring region may be coplanar with the first face of the insulating layer.

A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.