A semiconductor device package includes a first substrate, a second substrate, a first support element, a second support element and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The first substrate has a conductive pad adjacent to the first surface of the first substrate. The second substrate is disposed over the first surface of the first substrate. The first support element is disposed between the first substrate and the second substrate. The first support element is disposed adjacent to an edge of the first surface of the first substrate. The second support element is disposed between the first substrate and the second substrate. The second support element is disposed far away from the edge of the first surface of the first substrate. The electronic component is disposed on the second surface of the first substrate. A projection line of a contact point between the second support element and the conductive pad on the second surface of the first substrate is physically spaced apart from a projection line of a lateral surface of the electronic component on the second surface of the first substrate.

An electronic component module includes a second terminal electrode that is independent of a first terminal electrode in terms of potential. A second electronic component is mounted on a board, with a first surface thereof facing the board. A heat transfer portion is disposed on a second surface of the second electronic component, the heat transfer portion being connected to both the first terminal electrode and the second terminal electrode. A heat dissipation portion is connected to the board via the first terminal electrode, the second terminal electrode, and the heat transfer portion.

A method and system of co-packaging optoelectronics components or photonic integrated circuit (PIC) with application specific integrated circuits (ASICs) are disclosed and may include package substrate, several electronics die, passive components, socket assembly, and heat sinks. The said method converts ASIC high speed signals to optical signals by eliminating intermediary electrical interface between the ASIC and conventional optical modules. The method described provides many advantages of pluggable optical modules such as configurability, serviceability, and thermal isolation from the ASIC heat, while eliminating bandwidth bottlenecks as result of the ASIC package, host or linecard printed circuit board (PCB) traces, and the optical module connector. The high-power consumption ASIC is mounted below the package substrate, but sensitive optoelectronics and PIC components are mounted on top of the package substrate assembly for thermal isolation and serviceability. The package assembly ball grid array (BGA) or pin grid array (PGA) contacts are on the same side of the package substrate surface as ASIC die. The co-packaged package assembly is attached to the host or linecard PCB having a cutout for ASIC with the heatsink mounted from the bottom onto the ASIC die.

A semiconductor device package includes a first substrate, a second substrate, a first support element, a second support element and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The first substrate has a conductive pad adjacent to the first surface of the first substrate. The second substrate is disposed over the first surface of the first substrate. The first support element is disposed between the first substrate and the second substrate. The first support element is disposed adjacent to an edge of the first surface of the first substrate. The second support element is disposed between the first substrate and the second substrate. The second support element is disposed far away from the edge of the first surface of the first substrate. The electronic component is disposed on the second surface of the first substrate. A projection line of a contact point between the second support element and the conductive pad on the second surface of the first substrate is physically spaced apart from a projection line of a lateral surface of the electronic component on the second surface of the first substrate.

In a power semiconductor module, a first conductive layer including first to fourth electrodes are formed on one of principal surfaces of an insulating layer, and a conductive substrate functioning as a second conductive layer is formed on the other one of principal surfaces. Current paths are switched by controlling switching of a first transistor and a second transistor disposed on a surface of the first conductive layer thereby performing a power conversion. A capacitor is connected, in a region, between the first electrode and the second electrode. When a current flows in the region through the second conductive layer, a charging/discharging current occurs in the capacitor, which results in magnetic field cancellation.

The invention provides a circuit pin positioning structure, a fabrication method of soldered circuit elements and a method of forming circuit pins of a stacked package, applicable to a semiconductor package structure. A positioning rack and a plurality of conductor elements are used. A plurality of positioning holes are provided on a bottom surface of the positioning rack to form a conductor positioning area, and an operational portion is formed on an opposing surface away from the conductor positioning area, for being mounted with pick and place equipment. The conductor elements are positioned in the positioning holes. When the pick and place equipment loads and moves the positioning rack to preformed circuit contacts of the stacked package, the conductor elements are soldered to the preformed circuit contacts and then the positioning rack is removed.

A method includes surrounding a die and a conductive pillar proximate the die with a molding material, where the die and the conductive pillar are disposed over a first side of a first redistribution structure, where a second side of the first redistribution structure opposing the first side is attached to a first carrier; bonding conductive pads disposed on a first surface of a pre-made second redistribution structure to the die and to the conductive pillar, where a second surface of the pre-made second redistribution structure opposing the first surface is attached to a second carrier; after bonding the conductive pads, removing the second carrier to expose conductive features of the pre-made second redistribution structure proximate the second surface; and forming conductive bumps over and electrically coupled to the conductive features of the pre-made second redistribution structure.

An antenna that is formed of a conductor pattern is disposed on a dielectric substrate. A high-frequency semiconductor device that supplies a high-frequency signal to the antenna is mounted on the bottom surface of the dielectric substrate. A plurality of conductor columns project from the bottom surface. The conductor columns are embedded in a dielectric member that is disposed on the bottom surface. An end of each of the conductor columns is exposed through the dielectric member. The dielectric member defines a mounting surface that faces a mounting substrate. A step is formed in a side surface of a composite structure that includes the dielectric substrate and the dielectric member, and a side surface extending from the mounting surface to the step is more recessed than a side surface that is located above the step.

Package structures are provided having antenna-in-packages that are integrated with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems that operate in the millimeter wave (mmWave) frequency range with radiation in broadside and end-fire directions.

An electronic package is provided, which stacks an electronic structure as an integrated voltage regulator on an electronic component to facilitate close-range cooperation with the electronic component for electrical transmission.