One aspect relates to a method for producing a substrate plate for a large-area semiconductor element, particularly for a thyristor wafer or a diode. At least one first layer made from a first material, with a first coefficient of expansion, and at least one second layer made from a second material of low expandability, with a second coefficient of expansion, which is smaller than the first coefficient of expansion, are bonded to one another by means of a low-temperature sintering method at a bonding temperature of 150° C.-300° C. At least one first bonding layer made from a bonding material is formed between the first layer and the second layer and the bonding temperature substantially corresponds to the mounting temperature during the bonding of the substrate plate produced with at least one large-area semiconductor element.

A semiconductor element bonding structure capable of strongly bonding a semiconductor element and an object to be bonded and relaxing thermal stress caused by a difference in thermal expansion, by interposing metal particles and Ni between the semiconductor element and the object to be bonded, the metal particles having a lower hardness than Ni and having a micro-sized particle diameter. A plurality of metal particles 5 (aluminum (Al), for example) having a lower hardness than nickel (Ni) and having a micro-sized particle diameter are interposed between a semiconductor chip 3 and a substrate 2 to be bonded to the semiconductor chip 3, and the metal particles 5 are fixedly bonded by the nickel (Ni). Optionally, aluminum (Al) or an aluminum alloy (Al alloy) is used as the metal particles 5, and aluminum (Al) or an aluminum alloy (Al alloy) is used on the surface of the semiconductor chip 3 and/or the surface of the substrate 2.

A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.

A method of fabricating a packaging substrate is provided, which includes: forming on a carrier a conductor layer having a plurality of openings; forming a plurality of conductive bumps on the conductor layer, wherein each of the conductive bumps has a post body disposed in a corresponding one of the openings and a conductive pad disposed on the conductor layer, the post body being integrally formed with the conductive pad and less in width than the conductive pad; forming a plurality of conductive posts on the conductive pads; forming on the carrier a first insulating layer that encapsulates the conductive bumps and the conductive posts; removing the carrier; and removing the entire conductor layer to expose the post bodies from a first surface of the first insulating layer. As such, a semiconductor chip can be bonded to the packaging substrate through the conductive bumps.

A thermosetting silicone resin composition contains the following components (A-1) to (D): (A-1) an alkenyl group-containing linear organopolysiloxane; (A-2) a branched organopolysiloxane shown by (R.sup.1.sub.3SiO.sub.1/2).sub.a(R.sup.2.sub.3SiO.sub.1/2).sub.b(SiO.sub.4/2).sub.c (1) ; (B-1) a branched organohydrogenpolysiloxane shown by (HR.sup.2.sub.2SiO.sub.1/2).sub.d(R.sup.2.sub.3SiO.sub.1/2).sub.e(SiO.sub.4/2).sub.f (2) ; (B-2) a linear organohydrogenpolysiloxane shown by (R.sup.2.sub.3SiO.sub.1/2).sub.2(HR.sup.2SiO.sub.2/2).sub.x(R.sup.2.sub.2SiO.sub.2/2).sub.y (3) ; (C) an adhesion aid which is an epoxy group-containing branched organopolysiloxane; and (D) a catalyst containing a combination of a zero-valent platinum complex with a divalent platinum complex and/or a tetravalent platinum complex. This provides a thermosetting silicone resin composition which causes little contamination at a gold pad portion and has excellent adhesiveness to a silver lead frame.

A semiconductor device, including a conductive plate having a front surface that includes a plurality of bonding regions and a plurality of non-bonding regions in peripheries of the bonding regions, a plurality of semiconductor elements mounted on the conductive plate in the bonding regions, and a resin encapsulating therein at least the plurality of semiconductor elements and the front surface of the conductive plate. The conductive plate has, at the front surface thereof in the non-bonding regions, a plurality of holes.

A method of forming a chip package is provided. The method includes providing a malleable carrier with a layer of an electrically conductive material formed thereon, and positive fitting the malleable carrier to a chip to at least partially enclose the chip with the malleable carrier. The layer at least partially physically contacts the chip, such that the layer electrically contacts a chip contact of the chip. The layer forms a redistribution layer.

A semiconductor substrate includes a dielectric layer, a first conductive layer, a first barrier layer and a conductive post. The dielectric layer has a first surface and a second surface opposite to the first surface. The first conductive layer is disposed adjacent to the first surface of the dielectric layer. The first barrier layer is disposed on the first conductive layer. The conductive post is disposed on the first barrier layer. A width of the conductive post is equal to or less than a width of the first barrier layer.

Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.

Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.