METHOD FOR PRODUCING A SUBSTRATE PLATE, SUBSTRATE PLATE, METHOD FOR PRODUCING A SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE

Abstract

One aspect relates to a method for producing a substrate plate for a large-area semiconductor element, particularly for a thyristor wafer or a diode. At least one first layer made from a first material, with a first coefficient of expansion, and at least one second layer made from a second material of low expandability, with a second coefficient of expansion, which is smaller than the first coefficient of expansion, are bonded to one another by means of a low-temperature sintering method at a bonding temperature of 150° C.-300° C. At least one first bonding layer made from a bonding material is formed between the first layer and the second layer and the bonding temperature substantially corresponds to the mounting temperature during the bonding of the substrate plate produced with at least one large-area semiconductor element.

Claims

1-20. (canceled)

21. A method for producing a substrate plate for a large-area semiconductor element, comprising, bonding together at least one first layer made from a first material, having a first coefficient of expansion and at least one second layer made from a second material of low expandability, having a second coefficient of expansion that is smaller than the first coefficient of expansion; wherein the layers are bonded to one another by means of a low-temperature sintering method at a bonding temperature of 150° C.-300° C.; and forming at least one first bonding layer made from a bonding material between the first layer and the second layer, and the bonding temperature substantially corresponds to a mounting temperature during the bonding of the substrate plate produced with at least one large-area semiconductor element.

22. The method of claim 21, wherein the bonding temperature is between 240° C.-260° C.

23. The method of claim 21, wherein the bonding material of the bonding layer creates a bond that withstands temperatures above the bonding temperature and has a diffusion metal comprising one of a group comprising silver (Ag), a silver alloy, gold (Au), a gold alloy, copper (Cu), and a copper alloy.

24. The method of claim 21, wherein the first material has metal comprising one of a group comprising copper (Cu) and a copper alloy, and the second material has a nickel alloy comprising one of a group comprising Invar (Fe.sub.65Ni.sub.35), Invar 36 (Fe.sub.64Ni.sub.36), Kovar (Fe.sub.54Ni.sub.29Co.sub.17), tungsten (W), an iron-nickel-cobalt alloy (FeNiCo alloy), and molybdenum (Mo).

25. The method of claim 21, wherein the bonding at least of the first layer at least to the second layer and at least the first bonding layer takes place by means of the application of pressure between 10 MPa-28 MPa.

26. A substrate plate for a large-area semiconductor element, comprising: at least one first layer made from a first material, having a first coefficient of expansion; at least one second layer made from a second material of low expandability, having a second coefficient of expansion, which is smaller than the first coefficient of expansion; and at least one first bonding layer formed between the first layer and the second layer, wherein the first bonding layer comprises diffusion metal comprising one of a group comprising silver (Ag), a silver alloy, gold (Au), a gold alloy, copper (Cu), and a copper alloy.

27. The substrate plate of claim 26, wherein at least the first bonding layer is formed as a boundary layer of the first layer or the second layer.

28. The substrate plate of claim 26, wherein the first material has metal comprising one of a group comprising copper (Cu) and a copper alloy and the second material comprises one of a group comprising a nickel alloy, Invar (Fe.sub.65Ni.sub.35), Invar 36 (Fe.sub.64Ni.sub.36), Kovar (FesaNi.sub.29Co.sub.17), tungsten (W), an iron-nickel-cobalt alloy (FeNiCo alloy), and molybdenum (Mo).

29. The substrate plate of claim 26, wherein at least one third layer comprises the first material, which is bonded by means of a second bonding layer comprising the bonding material, to the second layer comprising the second material of low expandability.

30. The substrate plate of claim 29, wherein at least one fourth layer comprising the second material, which is bonded by means of a third bonding layer comprising the bonding material, to the third layer comprising the first material.

31. The substrate plate of claim 29, wherein the individual layers and bonding layers are symmetrical arranged in such a manner that a flat substrate plate is formed.

32. The substrate plate of claim 29, wherein the individual layers and bonding layers are asymmetrical arranged in such a manner that a convexly or concavely shaped substrate plate is formed.

33. The substrate plate of claim 29, wherein the first layer, the second layer, and the third layer, have different layer thicknesses.

34. The substrate plate of claim 30, wherein the second layer and at least the fourth layer is embedded in a layer comprising the first material.

35. The substrate plate of claim 26, wherein the second layer and the first layer are formed in one of a frame-like, grid-like, and wire-like manner.

36. A method for producing a semiconductor module, comprising forming a substrate plate, comprising: bonding together at least one first layer made from a first material, having a first coefficient of expansion and at least one second layer made from a second material of low expandability, having a second coefficient of expansion that is smaller than the first coefficient of expansion; wherein the layers are bonded to one another by means of a low-temperature sintering method at a bonding temperature of 150° C.-300° C.; and forming at least one first bonding layer made from a bonding material between the first layer and the second layer, and the bonding temperature substantially corresponds to a mounting temperature during the bonding of the substrate plate produced with at least one large-area semiconductor element; providing at least one large-area semiconductor element comprising one of a thyristor wafer and a diode; and boding the large-area semiconductor element, by means of a contacting layer, to the substrate plate at a mounting temperature of 150° C.-300° C., wherein the mounting temperature substantially corresponds to the bonding temperature during the bonding of the layers of the substrate plate.

37. The method of claim 36, wherein the bonding of the layers of the substrate plate and the bonding of the large-area semiconductor element to the substrate plate take place simultaneously.

38. The method of claim 36, wherein the mounting temperature is between 240° C.-260° C.

39. A semiconductor module comprising: a substrate plate, comprising: at least one first layer made from a first material, having a first coefficient of expansion; at least one second layer made from a second material of low expandability, having a second coefficient of expansion, which is smaller than the first coefficient of expansion; and at least one first bonding layer formed between the first layer and the second layer, wherein the first bonding layer comprises diffusion metal comprising one of a group comprising silver (Ag), a silver alloy, gold (Au), a gold alloy, copper (Cu), and a copper alloy; and at least one large-area semiconductor element comprising one of a thyristor wafer and a diode.

40. The semiconductor module of claim 39, wherein the large-area semiconductor element is bonded to the first layer of the substrate plate by means of a contacting layer.

Description

[0063] The invention is explained in more detail in the following with further details and with reference to the attached schematic drawings on the basis of exemplary embodiments. In the figures:

[0064] FIG. 1a shows the arrangement of individual layers and components of a semiconductor module according to the invention according to a first exemplary embodiment;

[0065] FIG. 1b shows the semiconductor module according to FIG. 1a in the bonded state;

[0066] FIG. 2a shows the arrangement of individual layers and components of a semiconductor module according to the invention according to a second embodiment; and

[0067] FIG. 2b shows the semiconductor module according to FIG. 2a in the bonded state.

[0068] In the following, the same reference numerals are used for the same parts and parts with the same action.

[0069] The individual layers and components of a semiconductor module 100 (see FIG. 1b) to be produced are illustrated in FIG. 1a. The semiconductor module 100 consists of the large-area semiconductor element 90 and the substrate plate 10. The substrate plate 10 comprises a first layer 20 made from a first material M1 and a second layer 30 made from a second material M2. The material M1 is preferably metal, particularly copper or a copper alloy. The material M2 is by contrast a material of low expandability with a second coefficient of expansion, which is lower than the first coefficient of expansion of the first material M1. The second material M2 may be a nickel alloy, particularly Invar or Invar 36 or Kovar and/or tungsten and/or an iron-nickel-cobalt alloy. In the present exemplary embodiment, the material M2 is molybdenum. A first bonding layer 40 made from a bonding material VM is formed between the first layer 20 and the second layer 30. The bonding material VM of the bonding layer 40 creates a bond between the first layer 20 and the second layer 30, which withstands temperatures above a bonding temperature. The bonding layer preferably has diffusion metal, particularly silver and/or a silver alloy and/or gold and/or a gold alloy and/or copper and/or a copper alloy.

[0070] The bonding layer is preferably formed as a sinter layer, particularly as a sinter paste. This sinter paste, which preferably has one of the listed diffusion metals, particularly silver and/or a silver alloy and/or silver carbonate and/or silver oxide, can for example be applied by means of a printing method onto the second side 22 of the first layer 20 and/or onto the first side 31 of the second layer 30. In the bonded state of the substrate plate 10, the first side 21 of the first layer 20 faces the large-area semiconductor element 90. The second side 22 of the first layer 20 faces the second layer 30 by contrast. In the bonded state, the first side 31 of the second layer 30 faces the first layer 20. The second side 32 of the second layer 30 is by contrast formed facing away from the first layer 20. The layer thickness d1 of the first layer 20 is at least twice as large as the layer thickness d2 of the second layer 30. Preferably, the layer thickness d1 is between 0.2 mm and 3.0 mm, whereas the layer thickness d2 is between 0.1 mm and 2.0 mm. The thickness of the first bonding layer 40 is preferably between 1 μm and 50 μm.

[0071] With the aid of the axis of symmetry S drawn in FIG. 1b it becomes clear that the structure of the substrate plate 10 is an asymmetrical structure of the individual layers 20, 30 and 40. The axis of symmetry S halves the total thickness D of the substrate plate 10. The total thickness D is formed by means of the addition of the layer thicknesses d1 and d2 and the layer thickness of the first bonding layer 40. With the aid of a substrate plate 10 which is asymmetric in this manner, a flat semiconductor module 100 in particular can be produced.

[0072] In the example illustrated, the large-area semiconductor element 90 is a silicon semiconductor formed as a thyristor. The width bHL of the semiconductor element 90 is only slightly smaller than the width bSP of the substrate plate. In the example illustrated, the large-area semiconductor element 90 is bonded to the substrate plate 10 by means of a contacting layer 50. The contacting layer 50 may in principle be an adhesive layer, a sinter-paste layer or a solder layer. In the present case, all layers 20, 30 and 40 are bonded to the large-area semiconductor element 90 and the contacting layer 50 simultaneously, so that the contacting layer 50 is preferably formed equivalently to the first bonding layer 40. The first bonding layer 40 and the contacting layer 50 are preferably a sinter paste.

[0073] Preferably, the layers 20, 30, 40, 50 and the large-area semiconductor element 90 are bonded to one another by means of a low-temperature sintering method at a bonding temperature of 150° C. to 300° C. The bonding temperature is particularly preferably 250° C.

[0074] The bonding of the layers 20, 30, 40, 50 to the large-area semiconductor element 90 preferably takes place by means of the application of pressure, particularly at a pressure of 5 MPa to 30 MPa, particularly of 10 MPa to 28 MPa, particularly of 25 MPa.

[0075] Alternatively, the large-area semiconductor element 90 can be applied to a previously produced substrate plate 10 in a separate mounting step. To this end, the large-area semiconductor element 90 is applied onto the first side 21 of the first layer 20 of the substrate plate 10 with the aid of the contacting layer 50. The surface 21 of the substrate plate 10 to be bonded to the semiconductor element is the first side 21 of the first layer 20.

[0076] To bond the large-area semiconductor element 90 to a previously produced substrate plate 10, the arrangement is loaded with a mounting temperature of 150° C. to 300° C., wherein this mounting temperature substantially corresponds to the bonding temperature during the bonding of the layers 20, 30 and 40 of the substrate plate 10.

[0077] A second embodiment with regards to a semiconductor module 100 to be produced (cf. FIG. 2b) is illustrated in FIGS. 2a and 2b. This is likewise an asymmetric structure of the substrate plate 10.

[0078] The substrate plate 10 consists of a first layer 20, a second layer 30 and a third layer 25. The first layer 20 and the third layer 25 have a first material M1. The material is preferably copper. A second layer 30 made from the second material M2 is formed between these two layers 20 and 25, which have different layer thicknesses d1 and d3. The second material M2 consists of a material of low expandability or the coefficient of expansion of the second material M2 is lower than the coefficient of expansion of the first material M1. The second material M2 is preferably molybdenum.

[0079] The indicated axis of symmetry S shows that the substrate plate 10 according to FIG. 2a or 2b is also an asymmetric structure of the same. A first bonding layer 40 is formed between the first layer 20 and the second layer 30. This bonding layer 40 is preferably a sinter layer, which has a bonding material VM, preferably silver. A second bonding layer 41 is formed between the second layer 30 and the third layer 25. This bonding layer 41 is preferably likewise a sinter layer, which has a bonding material VM, namely silver.

[0080] An adhesion-improving layer 60 is preferably applied on the first side 26 of the third layer 25 (cf. FIG. 2a). The first side 26 of the third layer 25 is the side of the third layer 25 facing the second layer 30. The adhesion-improving layer 60 is preferably electroplated onto the third layer 25. The adhesion-improving layer 60 is a silver layer for example. The adhesion between the third layer 25 and the second bonding layer 41 can be improved with the aid of the adhesion-improving layer 60.

[0081] In the joined state, a combined bonding layer 45 is present (cf. FIG. 2b). With the aid of a low-temperature sintering method, the second bonding layer 41 and the adhesion-improving layer 60 are pressed together so that the combined bonding layer 45 is formed.

[0082] The large-area semiconductor element 90 is in turn applied with the aid of the contacting layer 50 onto the first side 21 of the first layer 20.

[0083] Also, in connection with the exemplary embodiment according to FIGS. 2a and 2b it is possible to see that the layer thickness d1 of the first layer 20 is multiple-times larger than the layer thickness d2 of the second layer 30 made from material M2 of low expandability. The layer thickness d1 of the first layer 20 is likewise larger than the layer thickness d3 of the third layer 25 made from the first material M1.

[0084] The second layer 30 made from second material M2 of low expandability is formed asymmetrically inside the layer stack. An asymmetric placement of the second layer 30 of low expandability has the advantage that an axis of symmetry results in a targeted manner from the expansion of the large-area semiconductor element 90, particularly the silicon semiconductor element, and the expansion of the coated substrate plate 10. A planar contour of the semiconductor module 100 can finally be achieved, depending on the thickness dHL of the large-area semiconductor element 90 by means of the position of the second layer 30 made from material M2 of low expandability after the cooling.