Patent classifications
H01L2924/15787
Semiconductor apparatus and manufacturing method of semiconductor apparatus
A semiconductor apparatus includes: an insulating substrate including a circuit pattern; a semiconductor device mounted on the insulating substrate and electrically connected to the circuit pattern; a case storing the insulating substrate and the semiconductor device; and an electrode attached to the case, wherein a tip surface of the electrode is jointed to the circuit pattern with solder, the electrode is brought into contact with and pushed against the circuit pattern by the case, and a projection is provided on the tip surface.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes: a metal sheet; an insulating pattern provided on the metal sheet; a power circuit pattern and a signal circuit pattern that are provided on the insulating pattern; a power semiconductor chip mounted on the power circuit pattern; and a control semiconductor chip that is mounted on the signal circuit pattern and controls the power semiconductor chip. The power semiconductor chip is bonded to the power circuit pattern with a first die bonding material comprised of copper, and the control semiconductor chip is bonded to the signal circuit pattern with a second die bonding material.
Semiconductor device
A semiconductor device includes: a semiconductor chip; a case having a frame portion that has an inner wall portion surrounding an housing area in which the semiconductor chip is disposed; a buffer member provided on at last part of the inner wall portion of the case on a side of the housing area; a low expansion member provided on said at least part of the inner wall portion with the buffer member interposed therebetween on the side of the housing area; and a sealing member that seals the housing area, wherein the buffer member has a smaller elastic modulus than the case and the sealing member, and wherein the low expansion member has a smaller linear expansion coefficient than the case and the sealing member.
Mirror-image chips on a common substrate
An electronic device includes a substrate having contact pads disposed thereon and traces interconnecting the contact pads. A first integrated circuit (IC) die is mounted on the substrate and includes a predefined set of circuit components arranged on the first IC die in a first geometrical pattern, which is non-symmetrical under reflection about a given axis in a plane of the die. A second IC die is mounted on the substrate and includes the predefined set of circuit components arranged on the second IC die in a second geometrical pattern, which is a mirror image of the first geometrical pattern with respect to the given axis.
CERAMIC LAMINATED SUBSTRATE, MODULE, AND METHOD OF MANUFACTURING CERAMIC LAMINATED SUBSTRATE
Provided is a ceramic laminated substrate which is formed on an electronic component to be mounted and is less likely to cause mounting defects even if there is irregularity in the height of solders. The ceramic laminated substrate includes: a ceramic laminate on which ceramic layers are laminated; via conductors; terminal electrodes; and a land electrode. The land electrode has a first land electrode and a second land electrode that are used to join different terminal electrodes of a single electronic component. The area of the first land electrode is smaller than the area of the second land electrode, and the first land electrode has a bump electrode and a plating layer, the second land electrode has a membrane electrode and plating layers, and the height of the first land electrode is formed higher than the height of the second land electrode.
Illumination apparatus
An illumination apparatus comprises a plurality of LEDs aligned to an array of directional optical elements wherein the LEDs are substantially at the input aperture of respective optical elements. An electrode array is formed on the array of optical elements to provide at least a first electrical connection to the array of LED elements. Advantageously such an arrangement provides low cost and high efficiency from the directional LED array.
Illumination apparatus
An illumination apparatus comprises a plurality of LEDs aligned to an array of directional optical elements wherein the LEDs are substantially at the input aperture of respective optical elements. An electrode array is formed on the array of optical elements to provide at least a first electrical connection to the array of LED elements. Advantageously such an arrangement provides low cost and high efficiency from the directional LED array.
Electronic component, method for manufacturing the electronic component, and circuit board
A camera module includes an image sensor IC including terminal electrodes, and a circuit board on which the image sensor IC is mounted. The circuit board includes mount electrodes to which the terminal electrodes are ultrasonically welded, a flat film member provided with the mount electrodes, and a base member to which the flat film member is bonded. An elastic modulus of the flat film member is higher than that of the base member.
Electronic component, method for manufacturing the electronic component, and circuit board
A camera module includes an image sensor IC including terminal electrodes, and a circuit board on which the image sensor IC is mounted. The circuit board includes mount electrodes to which the terminal electrodes are ultrasonically welded, a flat film member provided with the mount electrodes, and a base member to which the flat film member is bonded. An elastic modulus of the flat film member is higher than that of the base member.
Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
An apparatus relating generally to a die stack is disclosed. In such an apparatus, a substrate is included. A first bond via array includes first wires each of a first length extending from a first surface of the substrate. An array of bump interconnects is disposed on the first surface. A die is interconnected to the substrate via the array of bump interconnects. A second bond via array includes second wires each of a second length different than the first length extending from a second surface of the die.