Patent classifications
H01L2924/15788
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate, a redistribution layer (RDL) including a dielectric layer disposed over the substrate and a plurality of conductive members surrounded by the dielectric layer, a first conductive pillar disposed over and electrically connected with one of the plurality of conductive members, a second conductive pillar disposed over and electrically connected with one of the plurality of conductive member, a first die disposed over the RDL and electrically connected with the first conductive pillar, and a second die disposed over the RDL and electrically connected with the second conductive pillar, wherein a height of the second conductive pillar is substantially greater than a height of the first conductive pillar, and a thickness of the first die is substantially greater than a thickness of the second die.
METHOD OF MANUFACTURING MOUNTING SUBSTRATE AND MOUNTING SUBSTRATE MANUFACTURING APPARATUS
A method of manufacturing a mounting substrate includes a provisional pressing process, a driver pressing process, and a flexible printed circuit board pressing process. In the provisional pressing process, a driver 40 and a flexible printed circuit board are provisionally pressed. In the driver pressing process, the driver 40 is thermally pressed with using a pressing head 52 having a driver pressing surface 53 and a flexible printed circuit board pressing surface 54, and pressure force is applied to the driver 40 with elastically deforming a buffer 57. In the flexible printed circuit board pressing process, the pressing head 52 is moved closer to the glass substrate GS such that a height level of the flexible printed circuit board pressing surface 54 with respect to a mounting surface 21 and a height level of the driver pressing surface 53 with respect to the mounting surface 21 are same and pressure force is applied to the flexible printed circuit board 30 with elastically deforming the buffer 57.
Method of forming a chip assembly with a die attach liquid
A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.
Driving chip and display device
A driving chip and a display device, relating to the technical field of driving chip for displays, are disclosed. A surface of the driving chip has a first edge and a second edge opposite to each other. The driving chip includes connecting bumps and supporting bumps, which are arranged along the first edge to form at least one first bump column, and at either end of the first bump column, there is at least one of the supporting bumps; the connecting bumps and the supporting bumps are arranged along the second edge to form at least one second bump column, and at either end of the second bump column, there is at least one of the supporting bumps. A surface of the driving chip according to embodiments of the invention has bump columns, a supporting bump is disposed at an end of a bump column, and acts to support the driving chip favorably. Thus, upon bonding and packaging, the driving chip can bear a force in equilibrium as a whole, and occurrence of a problem of impression defectiveness is avoided.
Integrated circuit package substrate
Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A method of manufacturing a semiconductor structure includes the following operations. A substrate is provided. A first conductive pillar, a second conductive pillar arid a third conductive pillar are disposed over the substrate. The first conductive pillar comprises a first height, the second conductive pillar comprises a second height, and the third conductive pillar comprises a third height. A first die is disposed over the first conductive pillar. A second die is disposed over the second conductive pillar. A first surface of the first die and a second surface of the second die are at substantially same level.
STACKED DIES AND METHODS FOR FORMING BONDED STRUCTURES
In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.
Adhesive film and method for manufacturing semiconductor device
An adhesive film of the present invention includes a base material layer and a self-peeling adhesive layer laminated therein. The base material layer has a thermal contraction percentage in a direction of flow (thermal contraction percentage in an MD direction) and a thermal contraction percentage in an orthogonal direction with respect to the direction of flow (thermal contraction percentage in a TD direction) that satisfy the following conditions: (1) after heating at 150° C. for 30 minutes, 0.4≦|thermal contraction percentage in MD direction/thermal contraction percentage in TD direction|≦2.5 and average of thermal contraction percentage in MD direction and thermal contraction percentage in TD direction≦2%, and (2) after heating at 200° C. for 10 minutes, 0.4≦|thermal contraction percentage in MD direction/thermal contraction percentage in TD direction|≦2.5 and average of thermal contraction percentage in MD direction and thermal contraction percentage in TD direction≧3%.
Adhesive film and method for manufacturing semiconductor device
An adhesive film of the present invention includes a base material layer and a self-peeling adhesive layer laminated therein. The base material layer has a thermal contraction percentage in a direction of flow (thermal contraction percentage in an MD direction) and a thermal contraction percentage in an orthogonal direction with respect to the direction of flow (thermal contraction percentage in a TD direction) that satisfy the following conditions: (1) after heating at 150° C. for 30 minutes, 0.4≦|thermal contraction percentage in MD direction/thermal contraction percentage in TD direction|≦2.5 and average of thermal contraction percentage in MD direction and thermal contraction percentage in TD direction≦2%, and (2) after heating at 200° C. for 10 minutes, 0.4≦|thermal contraction percentage in MD direction/thermal contraction percentage in TD direction|≦2.5 and average of thermal contraction percentage in MD direction and thermal contraction percentage in TD direction≧3%.
Flip-chip, face-up and face-down centerbond memory wirebond assemblies
A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.