Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.

Disclosed is a semiconductor package comprising a substrate, a semiconductor chip on the substrate, a molding layer on the substrate covering the semiconductor chip, and a shield layer on the molding layer. The shield layer includes a polymer in which a plurality of conductive structures and a plurality of nano-structures are distributed wherein at least some of the conductive structures are connected to one another.

A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.

Embodiments may relate to a microelectronic package comprising an integrated heat spreader (IHS) coupled with a package substrate. A sealant may be positioned between, and physically coupled to, the IHS and the package substrate. The sealant may at least partially extend from a footprint of the IHS. Other embodiments may be described or claimed.

In one example, an electronic device includes a substrate having a substrate top side, a substrate bottom side opposite to the substrate top side. A first electronic component is connected to the substrate top side and having a first electronic component top side distal to the substrate top side. A second electronic is connected to the substrate top side, laterally spaced apart from the first electronic component, and having a second electronic component top side distal to the substrate top side. A lid is connected to the substrate top side, covering the first electronic component and the second electronic component. The lid includes a lid ceiling; and a lid wall extending from the lid ceiling and defining a lid periphery. A dam structure is connected to the first electronic device top side and the lid ceiling within the lid periphery and having a vent. A first interface material is over the first electronic component top side and contained within the dam structure. A second interface material is over the second electronic component top side and connected to the lid ceiling, where the dam structure separates the first interface material from the second interface material. The first interface material has a higher thermal conductivity than the second interface material. Other examples and related methods are also disclosed herein.

A semiconductor device has a substrate and a first electrical component including a sensing region disposed over the substrate. The sensing region can be responsive to external stimuli, such as pressure. A cover lid is disposed over the first electrical component and extending to the substrate with an opening in the cover lid aligned over the sensing region. A gel material is disposed within the opening of the cover lid to seal the sensing region with respect to an environment condition, such as liquid. A bond wire is coupled between the first electrical component and substrate. An adhesive layer is disposed around a perimeter of the sensing area and the cover lid is bonded to the adhesive layer. A second electrical component is disposed on the substrate and the first electrical component is disposed on the second electrical component.

Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.

A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.