Electrical package including bimetal lid. The electrical package includes: an organic substrate; a semiconductor chip electrically connected to electrical pads on a surface of the organic substrate via a plurality of solder balls; and a lid for encapsulating the semiconductor chip on the organic substrate, wherein (i) an inner surface of a central part of the lid is connected to a surface of the semiconductor chip via a first TIM, (ii) an inner surface of an outer part of the lid is hermetically connected to the surface of the organic substrate, and (iii) the lid has a bimetal structure including at least two different metals. A circuit module is also provided.

A semiconductor device according to an embodiment includes: an insulating substrate having a first metal layer and a second metal layer; a semiconductor chip on the first metal layer having an upper electrode and a lower electrode connected to the first metal layer; a bonding wire having a first end portion connected to the upper electrode and a second end portion connected to the second metal layer; a first resin layer covering the semiconductor chip and the bonding wire, the first resin layer containing a first resin; a second resin layer covering a bonding portion between the first end portion and the upper electrode containing a second resin having a Young's modulus higher than that of the first resin; a third resin layer on the first resin layer, the third resin layer containing a third resin having a moisture permeability lower than that of the first resin.

Disclosed are chip packaging structures for high speed chip to chip and chip to carrier communications and methods of making such structures. The chip packaging structures do not require an interposer containing through silicon vias and/or provide structures having reduced warping.

In embodiments described herein, an integrated circuit (IC) package is provided. The IC package may include a substrate, an IC die, and a heat spreader. The IC die may have opposing first and second surfaces, where the first surface of the IC die is coupled to a surface of the substrate. The heat spreader may have a surface coupled to the second surface of the IC die by a thermal interface (TI) material. The surface of the heat spreader may have a micro-recess which may include a micro-channel or a micro-dent to direct a flow of TI material towards or away from a predetermined area of the second surface of the IC die based on temperatures of the substrate, the IC die, and/or the heat spreader.

Apparatuses and methods for heat transfer from packaged semiconductor die are described. For example, an apparatus may include a plurality of die in a stack, and a barrier in close proximity to at least an edge of each of the plurality of die. The apparatus may further include fill material in spaces between adjacent die of the plurality of die and in between the plurality of die and the barrier.

An electronic package includes a carrier, semiconductor chip, a lid, and a lid-ring. The carrier includes a top surface and a bottom surface configured to be electrically connected to a system board. The semiconductor chip is electrically connected to the top surface. The lid is attached to the top surface enclosing semiconductor chip and includes a perimeter recess. The lid-ring is juxtaposed within the perimeter recess. The lid-ring exerts a reverse bending moment upon the lid to limit warpage of the electronic package.

Various embodiments relating to semiconductor package structures having reduced thickness while maintaining rigidity are provided. In one embodiment, a semiconductor package structure includes a substrate including a surface, a semiconductor die including a first interface surface connected to the surface of the substrate and a second interface surface opposing the first interface surface, a mold compound applied to the substrate surrounding the semiconductor die. The second interface surface of the semiconductor die is exposed from the mold compound. The semiconductor package structure includes a heat dissipation cover attached to the second interface surface of the semiconductor die and the mold compound.

Electrical package including bimetal lid. The electrical package includes: an organic substrate; a semiconductor chip electrically connected to electrical pads on a surface of the organic substrate via a plurality of solder balls; and a lid for encapsulating the semiconductor chip on the organic substrate, wherein (i) an inner surface of a central part of the lid is connected to a surface of the semiconductor chip via a first TIM, (ii) an inner surface of an outer part of the lid is hermetically connected to the surface of the organic substrate, and (iii) the lid has a bimetal structure including at least two different metals. A circuit module is also provided.

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.

A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.