A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip; a second interconnection member disposed on the first interconnection member and the semiconductor chip and including redistribution layers electrically connected to the connection pads of the semiconductor chip; a passivation layer disposed on the second interconnection member and having openings exposing at least portions of the redistribution layer of the second interconnection member; and an under-bump metal layer disposed on the passivation layer and filling at least portions of the openings. In the under-bump metal layer, the number of conductor layers formed on a surface of the passivation layer is different from that of conductor layers formed on the exposed redistribution layer and walls of the openings.

A semiconductor package includes a semiconductor die having an active surface and a bottom surface opposite to the active surface; a plurality of bond pads distributed on the active surface of the semiconductor die; an encapsulant covering the active surface of the semiconductor die, wherein the encapsulant comprises a bottom surface that is flush with the bottom surface of the semiconductor; and a plurality of printed interconnect features embedded in the encapsulant for electrically connecting the plurality of bond pads. Each of the printed interconnect features comprises a conductive wire and a conductive pad being integral with the conductive wire.

A package includes a chip, a wire, a mold layer and a redistribution layer. The chip includes a conductive pad. The wire is bonded to the conductive pad of the chip. The mold layer surrounds the first chip and the wire. The redistribution layer is disposed on the mold layer and contacts an exposed portion of the wire.

A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only.

A microelectronic package includes at least one microelectronic element having a front surface defining a plane, the plane of each microelectronic element parallel to the plane of any other microelectronic element. An encapsulation region overlying edge surfaces of each microelectronic element has first and second major surfaces substantially parallel to the plane of each microelectronic element and peripheral surfaces between the major surfaces. Wire bonds are electrically coupled with one or more first package contacts at the first major surface of the encapsulation region, each wire bond having a portion contacted and surrounded by the encapsulation region. Second package contacts at an interconnect surface being one or more of the second major surface and the peripheral surfaces include portions of the wire bonds at such surface, and/or electrically conductive structure electrically coupled with the wire bonds.

A chip card manufacturing method. A module includes a substrate supporting contacts on one surface and conductive paths and a chip on another; and an antenna on a holder, the antenna including a contact pad for respectively connecting to each of the ends thereof. A solder drop is placed on each of the contact pads of the antenna. The holder of the antenna is inserted between plastic layers. A cavity is provided, in which the module can be accommodated and the solder drops remain accessible. The height of the solder drops before heating is suitable for projecting into the cavity. A module is placed in each cavity. The areas of the module that are located on the solder drops are heated to melt the solder and to solder the contact pads of the antenna to conductive paths of the module.

Devices and methods are disclosed, related to shielding and packaging of radio-frequency (RF) devices on substrates. In some embodiments, A radio-frequency (RF) module comprises a lead-frame package with a plurality of pins and at least one pin exposed from overmold compound. The module further includes a metal-based covering over a portion of the lead-frame package. Additionally, the metal-based covering can be in contact with the at least one pin.

A substrate-less integrated electronic element module for a semiconductor package, comprising: at least two electronic elements, each of the at least two electronic elements having first electrical connectors; and a first molding compound encapsulating the at least two electronic elements, the first molding compound comprising a first planar surface and an opposing second planar surface of the integrated electronic element module, wherein each of the first electrical connectors is directly exposed on the first planar surface of the integrated electronic element module. Further, a semiconductor package including the integrated electronic element module and the method of fabricating the same is provided.

Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

A semiconductor device includes a semiconductor element, an electronic component electrically connected to the semiconductor element, a connection member electrically connecting the electronic component to the semiconductor element, and a sealing resin portion having a first surface and a second surface opposite to the first surface and integrally holding the semiconductor element, the electronic component, and the connection member in a state where a semiconductor top surface as a surface of the semiconductor element and a component surface as a surface of the electronic component are exposed from the sealing resin portion on a side adjacent to the first surface.