A semiconductor package includes a mold substrate, at least one first semiconductor chip in the mold substrate and including chip pads, wiring bonding pads formed at a first surface of the mold substrate and connected to the chip pads by bonding wires, and a redistribution wiring layer covering the first surface of the mold substrate and including redistribution wirings connected to the wiring bonding wirings.

Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

In one embodiment, a method includes: laser ablating an encapsulant of a semiconductor package, until a threshold amount of the encapsulant remains above one or more die of the semiconductor package; and providing at least one drop of acid onto a surface of the ablated semiconductor package to acid etch for a first time duration, to remove a remaining portion of the encapsulant above the one or more die, where after the acid etch, a die of interest is exposed and the silver bond wires of the semiconductor package are preserved.

There is provided a semiconductor device including: a conductive support including a first die pad and a second die pad having a potential different from a potential of the first die pad; a first semiconductor element mounted on the first die pad; a second semiconductor element mounted on the second die pad; and a sealing resin that covers the first semiconductor element, the second semiconductor element, and at least a portion of the conductive support.

Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

A semiconductor package includes a molding compound, a chip and a conductive pad, wherein the chip is electrically connected to the conductive pad and both are encapsulated in the molding compound. An anchor flange is formed around a top surface of the conductive pad by over plating. When the conductive pad is embedded in the molding compound, the anchor flange engages the molding compound to prevent the conductive pad from separation. Bottoms of a chip and the conductive pad are exposed from the molding compound for electrically soldering to a circuit board.

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

A microelectronic device, in a multirow gull-wing chip scale package, has a die connected to intermediate pads by wire bonds. The intermediate pads are free of photolithographically-defined structures. An encapsulation material at least partially surrounds the die and the wire bonds, and contacts the intermediate pads. Inner gull-wing leads and outer gull-wing leads, located outside of the encapsulation material, are attached to the intermediate pads. The gull-wing leads have external attachment surfaces opposite from the intermediate pads. The external attachment surfaces of the outer gull-wing leads are located outside of the external attachment surfaces of the inner gull-wing leads. The microelectronic device is formed by mounting the die on a carrier, forming the intermediate pads without using a photolithographic process, and forming the wire bonds. The encapsulation material is formed, and the carrier is subsequently removed, exposing the intermediate pads. The gull-wing leads are formed on the intermediate pads.

The semiconductor device A1 includes a support member 2, a metal part 30 having obverse and reverse surfaces 301-302 spaced in z direction, with the reverse surface 302 bonded to the support member 2, a second bonding layer 42 boding the support member 2 and the metal part 30, a semiconductor element 10 facing the obverse surface 301 and bonded to the metal part 30, and a sealing member 7 covering the support member 2, metal part 30, second bonding layer 42 and semiconductor element 10. The metal part 30 includes a first body 31 of a first material and a second body 32 of a second material, with a boundary between the bodies 31-32. The second material has a linear thermal expansion coefficient smaller than that of the first material. The semiconductor device is improved in reliability by reducing thermal stress from heat generation of the semiconductor element.