Structures and methods for reducing thermal expansion mismatch during chip scale packaging are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes a first metal layer over a substrate, a dielectric region, and a polymer region. The first metal layer comprises a first device metal structure. The dielectric region is formed over the first metal layer. The polymer region is formed over the dielectric region. The dielectric region comprises a plurality of metal layers and an inter-metal dielectric layer comprising dielectric material between each pair of two adjacent metal layers in the plurality of metal layers. Each of the plurality of metal layers comprises a dummy metal structure over the first device metal structure. The dummy metal structures in each pair of two adjacent metal layers in the plurality of metal layers shield respectively two non-overlapping portions of the first device metal structure from a top view of the semiconductor structure.

A semiconductor element includes first/second electrodes on an element obverse surface, an insulating layer on the element obverse surface, and first/second electrode terminals in contact with the first/second electrodes, respectively. The insulating layer includes first/second openings, and first/second overlapping portions adjoining the first/second openings, respectively. The first/second openings expose the first/second electrodes, respectively. The first/second overlapping portions overlap with the first/second electrodes, respectively, as viewed in a thickness direction. The first/second electrode terminals are in contact with the first/second electrodes, respectively, through the first/second openings, while also overlapping with the first/second overlapping portions as viewed in the thickness direction. The first electrode terminals are in a region with a high arrangement density of electrode terminals, whereas the second electrode terminals are in a region with a low arrangement density of electrode terminals. Each first overlapping portion has a greater dimension in the thickness direction than each second overlapping portion.

A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

There are provided a semiconductor module capable of preventing the peeling of a sealing resin on the side where a connection section used for the connection to a semiconductor element is arranged and a manufacturing method for a semiconductor module. A semiconductor module includes: an outer frame; sealing resins; gate signal output terminals, and partition sections laid across the outer flame to partition a space into a plurality of housing sections, in the partition sections which the gate signal output terminals with connection sections exposed are arranged. The partition sections have through holes where sealing resins are formed, the sealing resins connecting adjacent housing sections and the sealing resin formed in the through hole being continuous with the sealing resins formed in the housing sections.

A semiconductor package includes a base chip including a passivation layer on an upper surface thereof, a semiconductor chip on the base chip, a bump on a lower surface of the semiconductor chip, an underfill layer covering the bump and covering the lower surface of the semiconductor chip, an encapsulant covering the semiconductor chip on the base chip, and an organic material layer on the passivation layer, wherein the base chip includes silicon (Si), the passivation layer has a first region in contact with the underfill layer and a second region, surrounding the first region, and the organic material layer is on the second region.

A semiconductor device has an electrical component and a first TIM with a first compliant property is disposed over a surface of the electrical component. A second TIM having a second compliant property greater than the first compliant property is disposed over the surface of the electrical component within the first TIM. A third TIM can be disposed over the surface of the electrical component along the first TIM. A heat sink is disposed over the first TIM and second TIM. The second TIM has a shape of a star pattern, grid of dots, parallel lines, serpentine, or concentric geometric shapes. The first TIM provides adhesion for joint reliability and the second TIM provides stress relief. Alternatively, a heat spreader is disposed over the first TIM and second TIM and a heat sink is disposed over a third TIM and fourth TIM on the heat spreader.

A semiconductor device includes a semiconductor element, a lead frame, a conductive member, a resin composition and a sealing resin. The semiconductor element has an element front surface and an element back surface facing away in a first direction. The semiconductor element is mounted on the lead frame. The conductive member is bonded to the lead frame, electrically connecting the semiconductor element and the lead frame. The resin composition covers a bonded region where the conductive member and lead frame are bonded while exposing part of the element front surface. The sealing resin covers part of the lead frame, the semiconductor element, and the resin composition. The resin composition has a greater bonding strength with the lead frame than a bonding strength between the sealing resin and lead frame and a greater bonding strength with the conductive member than a bonding strength between the sealing resin and conductive member.

Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.

A wiring substrate includes: a first insulating layer; a first metal pattern formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover the first metal pattern; a second metal pattern formed on the second insulating layer; and an organic insulating film contacted with a portion of the second metal pattern. Also, the first metal pattern has: a first lower surface contacted with the first insulating layer; and a first upper surface contacted with the second insulating layer. Also, the second metal pattern has: a second lower surface contacted with the second insulating layer; and a second upper surface contacted with the organic insulating film. Further, a surface roughness of the second upper surface is larger than a surface roughness of each of the second lower surface, the first upper surface and the first lower surface.

Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises connection terminals between a first die and a second die. The first die has signal and peripheral regions and includes first vias on the peripheral region. The second die is on the first die and has second vias on positions that correspond to the first vias. The connection terminals connect the second vias to the first vias. The peripheral region includes first regions adjacent to corners of the first die and second regions adjacent to lateral surfaces of the first die. The connection terminals include first connection terminals on the first regions and second connection terminals on the second regions. A sum of areas of the first connection terminals per unit area on the first regions is greater than that of areas of the second connection terminals per unit area on the second regions.