The present disclosure relates to a non-volatile memory device and to a method for generating overvoltage values in such a memory device structured in a plurality of sub-arrays and including at least a decoding and sensing circuitry associated with each sub-array, a charge pump architecture for each sub-array including pump stages for increasing the value of an input voltage and obtaining an overvoltage output value, a control and JTAG interface in the memory device, and at least a registers block coupled to the charge pump architecture and driven by a logic circuit portion for receiving at least an activation signal selecting a specific charge pump architecture associated with a memory sub-array of the plurality of sub-arrays.

An electronic circuit includes a charge pump circuit, which includes a drive power supply; a flying capacitor; and a pump capacitor that is coupled in parallel to the drive power supply and the flying capacitor in response to a first control signal being in first state and is configured to receive charge from the flying capacitor to boost a pump voltage across the pump capacitor to a value that exceeds a drive voltage provided by the drive power supply responsive to a transition of the first control signal from the first state to a second state. The electronic circuit further includes a gate drive circuit coupled to the charge pump circuit.

Low noise charge pumps are disclosed. In certain embodiments, a charge pump includes a charge pump output terminal that provides a charge pump voltage, a switched capacitor, and a plurality of switches that charge the switched capacitor during a charging operation of the charge pump and that connect the switched capacitor to the charge pump output terminal during a discharging operation of the charge pump. The switches operate with non-overlap between the charging operation and the discharging operation so that the charge pump operates with low noise.

A charge pump circuit includes a first charge pump stage circuit coupled in series with a second charge pump stage circuit. A discharge circuit operates to discharge the charge pump circuit. The discharge circuit includes: a first switched circuit coupled to a first output of the first charge pump stage circuit and configured, when actuated, to discharge the first output; and a second switched circuit coupled to a second output of the second charge pump stage circuit and configured, when actuated, to discharge the second output. A discharge control circuit actuates the first switched discharge circuit to discharge the first output and then, after the first output is fully discharged, actuates the second switched discharge circuit to discharge the second output.

The charge transfer transistors of a positive or negative charge pump are biased at their gate terminals with a control voltage that provides for an higher level of gate-to-source voltage in order to reduce switch resistance in passing a boosted (positive or negative) voltage to a voltage output of the charge pump. This control voltage is generated using a bootstrapping circuit whose polarity of operation (i.e., negative or positive) is opposite to a polarity (i.e., positive or negative) of the charge pump.

A buck-boost switching regulator includes: a power switch circuit including an input switch unit and an output switch unit which switch a first terminal and a second terminal of an inductor for buck-boost conversion; at least one low dropout regulator correspondingly coupled to at least one output high side switch in the output switch unit to correspondingly convert at least one low dropout voltage into at least one output voltage; and a bypass control circuit configured to operably generate a bypass control signal according to a conversion voltage difference between the input voltage and the corresponding low dropout voltage; wherein when the corresponding conversion voltage difference is lower than a reference voltage, the bypass control signal controls a corresponding bypass switch to electrically connect the input voltage with the corresponding low dropout node.

A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes, two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first mode and a second mode when in use with two flying capacitors connected to the flying capacitor nodes, wherein at least the first mode corresponds to a bipolar output voltage of +/−3VV, +/−VV/5 or +/−VV/6.

A voltage monitoring circuit portion is arranged to monitor a negative supply voltage (V.sub.neg) and comprises a negative voltage generator arranged to generate the negative supply voltage (V.sub.neg) and to output the negative supply voltage (V.sub.neg) at an output terminal. A capacitor is arranged so that a first capacitor plate is connected to the output terminal of the generator and to a reference node via a potential divider. The potential divider is arranged to produce a monitor voltage (V.sub.monitor) between the resistors, where the reference node is supplied with a positive predetermined reference voltage (V.sub.ref). A comparator compares the monitor voltage (V.sub.monitor) to a threshold voltage (V.sub.ref_low) and to produce an output signal having a first value when the monitor voltage (V.sub.monitor) is below the threshold voltage (V.sub.ref_low) and having a second value otherwise. The negative voltage generator is enabled only when the output signal has its second value.

The present disclosure relates to a non-volatile memory device and to a method for generating overvoltage values in such a memory device structured in a plurality of sub-arrays and including: at least a decoding and sensing circuitry associated with each sub-array; a charge pump architecture for each sub-array including pump stages for increasing the value of an input voltage and obtaining an overvoltage output value; a control and JTAG interface in said memory device; at least a registers block coupled to said charge pump architecture and driven by a logic circuit portion for receiving at least an activation signal selecting a specific charge pump architecture associated with a memory sub-array of the plurality of sub-arrays.

A system and method for generating a low supply voltage and a high supply voltage from an input voltage, wherein the dependency of the high supply voltage magnitude on the magnitude of the input voltage is removed and the resulting high supply voltage magnitude is a multiple of the low supply voltage magnitude. The low supply voltage and the high voltage may be implemented in a power converter of a communication system comprising a plurality of subscriber line interface circuits (SLICs).