A method includes charging a capacitor of a power inverter to a direct current (DC) input voltage from an input terminal of the power inverter. The capacitor has first and second terminals. The method also includes providing a first voltage at an output terminal of the power inverter at a first time by controlling one of either: an output switch that selectively couples the output terminal to either the first terminal or the second terminal; or a set of input switches that selectively couple the first and second terminals to either the input terminal or a ground terminal. The method further includes providing a second voltage at the output terminal at a second time by controlling the other of the output switch or the set of input switches.

A Hybrid DC-DC switching converter architecture is described. The Hybrid architecture includes a capacitive converter cascaded by an inductive converter for a boost switching converter, and an inductive converter cascaded by a capacitive converter for a buck switching converter. A capacitor at an intermediate node and a switch in the capacitive converter are removed. Reducing the switching converter by one switch and one capacitor results in a smaller implementation area. A single regulation circuit and an inductor with a smaller saturation current (Isat) are used.

A multi-level direct current converter includes a direct current conversion unit, a switching unit, a voltage management unit, and a controller. The direct current conversion unit includes a flying capacitor, a first power transistor, and a second power transistor. A first end of the first power transistor is connected to a voltage input end of the multi-level direct current converter, a second end of the first power transistor is connected to a first end of the second power transistor by using the flying capacitor, and a second end of the second power transistor is connected to a reference ground.

A system includes a first device, a second device, and a power control block. The first device has a first power converter and a first resonator which has a first resonant capacitor and a first coil. The second device has a second power converter and a second resonator which has a second resonant capacitor and a second coil. The second power converter is coupled to a ratio-controllable power converter, and the first coil and the second coil are magnetically coupled. The power control block is configured to adjust the system frequency, the second power converter output voltage and the current in the first coil in coordination.

An the LED driving circuit, for driving an the LED load, includes: a bridge rectifier for rectifying an AC input voltage into a DC voltage; a serial capacitor voltage divider coupled to the bridge rectifier, including a plurality of serial capacitors; a half-bridge switch, coupled to the serial capacitor voltage divider; and a controller coupled to the half-bridge switch, for determining whether the DC voltage is higher than a threshold value and for controlling the half-bridge switch in a full-voltage mode or a half-voltage mode. In the full-voltage mode, the plurality of serial capacitors of the serial capacitor voltage divider synchronously supply power to the LED load. In the half-voltage mode, the plurality of serial capacitors of the serial capacitor voltage divider alternatively supply power to the LED load.

A power converter includes a plurality of switches coupled between an input bus and an output bus, a full bridge coupled between the output bus and ground, and a plurality of capacitors coupled between the plurality of switches and the full bridge, wherein one capacitor of the plurality of capacitors is connected to a midpoint of one leg of the full bridge through a switch.

A control circuit is configured to control a switched capacitor converter to operate in a pulse frequency modulation (PFM) mode. The control circuit includes a one-shot circuitry configured to generate a one-shot pulse to drive the switched capacitor converter to operate in the PFM mode. A PFM mode comparator is coupled to the one-shot circuitry, and is configured to trigger, based on an output voltage of the switched capacitor converter, the one-shot circuitry to generate the one-shot pulse. The switched capacitor converter may be controlled to enter or exit the PFM mode operation based on a trailing current of a flying capacitor of the switched capacitor converter, an output current of the switched capacitor converter, a charging time duration of the flying capacitor when the switched capacitor converter is operating in the PFM mode, or a PFM switching period of the switched capacitor converter operating in the PFM mode.

Techniques and mechanisms for generating an output voltage with a switched capacitor voltage converter (SCVR). In an embodiment, the SCVR comprises converter cores which are coupled in parallel via multiple buses including a first bus, which is to receive an input voltage, and a second bus with which the SCVR is to provide the output voltage based on the input voltage. A first converter core comprises a capacitor and a first hierarchical switch network (HSN) which is coupled between the capacitor and the multiple buses. The first HSN switchedly provides any of multiple conductive paths each between the capacitor and a different respective one of the multiple buses. Two or more of the conductive paths are each provided with at least one same switch circuit of the first HSN. In another embodiment, the first converter core comprises two HSNs which each have a respective branching tree topology.

A converter includes two switching stages coupled in series between positive and negative input terminals. A control circuit is configured for driving the switching stages based on an output voltage of the converter. A first switching stage includes two switches coupled in series between a positive input terminal and a first node. A capacitor and an inductor are coupled in series between the two switches and a positive output terminal. A third switch is coupled between a node between the capacitor and the inductor and the negative input terminal. A second capacitor is coupled between the first node and the negative input terminal. A second switching stage includes a second node coupled to the first node. Two additional electronic switches are coupled in series between the second node and the negative input terminal. A second inductor is coupled between the two additional switches and the positive output terminal.

Circuits/methods for controlling the startup of multiple parallel power converters that avoid inrush current or switch overstress in an added power converter or a power converter having fault conditions. Embodiments include node status detectors coupled to nodes within parallel-connected power converters to monitor voltage/current and configured in some embodiments to work in parallel with an output status detector measuring the startup output voltage of a power converter. With charge pump-based power converters, the node status detectors ensure that the power converter pump capacitors are charged while the output capacitor is charged as well. For such embodiments, a softstart period of startup may be considered finished if both the shared output capacitors and the power converter pump capacitors are charged to target values. Embodiments may also be used for fault detection during steady-state operation.