A single-phase device-multiplexing active power decoupling cascaded rectifier and control method thereof. The rectifier includes: n device-multiplexing active power decoupling H-bridge units that are cascaded, n≥2; each unit including: a bridge arm H1 and a bridge arm H2 connected in parallel, a decoupling capacitor branch formed by two capacitors connected in series, and a resistive load; a decoupling inductor being connected in series between a midpoint of the decoupling capacitor branch and a midpoint of bridge arm H2; and a bridge arm H1 of a first unit being sequentially connected in series to an inductor, resistor, and power supply, and then connected to a bridge arm H2 of a last unit. A power switch module of an H-bridge rectification unit is multiplexed, which not only realizes unit power factor rectification of the unit, but also provides a loop for secondary ripple power to achieve secondary ripple power decoupling control.

The present application provides a conversion system and a control method, including N power converters and N controllers, and N controllers one-to-one corresponds to the N power converters. In addition to receiving a first side current and a second side voltage of a corresponding power converter, each of the N controllers can also receive a neighboring direct current voltage signal which only reflects second side voltages of other M power converters in the conversion system, and perform voltage control on the corresponding power converter according to the received signal. The present application adopts fully distributed control, and does not need to set up a centralized controller. When parts of controllers fail, the other controllers can continue to work, so the reliability is higher.

The present application provides a conversion system and a control method, including N power converters and N controllers, where each power converter includes a first side and a second side, the first sides of the N power converters are electrically coupled in series, and currents flowing through the first sides of the N power converters are the same, the N controllers correspond to the N power converters one to one. Each controller contains a common-mode voltage loop and a current loop. The common-mode voltage loop is configured to receive a voltage reference signal and a voltage feedback signal, and output a given signal. The current loop is configured to receive the given signal, a current reference signal, and a first side current of a corresponding power converter, and output a common-mode control signal to modulate a first side voltage of the corresponding power converter.

A multilevel converter system is provided. The system includes a converter and a converter controller interfaced with the converter. The converter controller includes a voltage loop, a current loop, and a voltage compensation loop. The voltage loop is configured to receive first and second voltages from the first and second segments of the converter and a reference voltage. The current loop is configured to receive a current output of the converter, a reference current, and a balancing reference current. The voltage compensation loop is configured to receive the first and second voltages and a sign signal. The converter controller is configured to generate first and second pulse-width modulation (PWM) signals using output signals from the current loop and the output compensation signals from the voltage compensation loop. The PWM signals are configured to control the switches of the converter and to balance the first voltage with the second voltage.

Disclosed is a solid-state transformer having an uninterrupted operation ability under an AC/DC fault, in which bridge arms of a hybrid modular multilevel converter include half-bridge submodules and full-bridge submodules. The half-bridge submodules and the full-bridge submodules are connected with input ends of isolated dual-active-bridge converters via DC capacitors of the half-bridge submodules and full-bridge submodules; output ends of the isolated dual-active-bridge converters are connected in parallel to form a low-voltage DC bus; and a three-phase full-bridge inverter is connected to the low-voltage DC bus. The solid-state transformer may be provided with four ports including a medium-voltage AC port, a medium-voltage DC port, a low-voltage DC port and a low-voltage AC port which are beneficial to the interconnection of multi-voltage-level and multi-form AC/DC hybrid distribution grids. The solid-state transformer has the uninterrupted operation ability under the AC/DC fault.

A multi-level power converter comprising: n input stages (Ein_n), n being at least equal to 1, each input stage comprising n+1 identical input converters (CONVx_En) connected together, the input converters (CONVx_En) exhibiting an identical topology, chosen from among the architectures of the NPC (Neutral Point Clamped), ANPC (Active Neutral Point Clamped), NPP (Neutral Point Piloted) and SMC (Stacked Multicell Converter); an output stage (Eout) connected to the input stage of rank 1 and comprising an output converter (CONVs) supplied with a differential voltage (Vfloat) resulting from a first electrical potential applied to the output of a first input converter of the input stage of rank 1 and from a second electrical potential applied to the output of a second input converter of the input stage of rank 1, the output converter (CONVs) exhibiting a topology chosen from among an architecture with floating capacitor (FC), SMC (Stacked Multicell Converter), NPC (Neutral Point Clamped), NPP (Neutral Point Piloted) and ANPC (Active Neutral Point Clamped).

A power supply device includes a storage battery, a capacitor unit connected to the storage battery, a power converter including three phases connected to the storage battery in parallel, a control device configured to control a switching on and off of switching elements included in the three phases respectively, a first connection terminal connected to a P terminal of a DC charger and located between first and second switching elements in any one of the three phases, and a second connection terminal connected to an N terminal of the DC charger and located between third and fourth switching elements in another one of the three phases.

A bridge circuit with series-connected switches and associated control method. The bridge circuit has a first bridge arm and a second bridge arm coupled to a common node, the first bridge arm has a plurality of series-connected first main switches, each first main switch is coupled in parallel with an auxiliary module, each first auxiliary module has a clamping capacitor and an auxiliary switch, the first bridge arm receives a first main switch signal to control the plurality of series-connected first main switches, the second bridge arm receives a second main switch signal, the control method is sensing voltages of the clamping capacitors in the first bridge arm, correspondingly generating voltage sensing signals, and turning on at least one auxiliary switch for a predetermined time during a dead time according to a sorting result of the voltage sensing signals.

A power converter with an automatic balance mechanism of a flying capacitor is provided. The flying capacitor and a first terminal of an output inductor are connected to a switch circuit. Two terminals of an output capacitor are respectively connected to a second terminal of the output inductor and grounded. Two input terminals of an error amplifier are respectively connected to a node between the output capacitor and the output inductor, and coupled to a reference voltage. The error amplifier outputs an error amplified signal according to a voltage of the node and the reference voltage. A comparator circuit receives a ramp signal. A slope of the ramp signal is proportional to a voltage of the flying capacitor. The comparator circuit compares the ramp signal with the error amplified signal to output a comparison signal. The driving circuit drives the switch circuit according to the comparison signal.

Generalized circuit topology of voltage level multiplier modules (VLMMs) for use with multilevel inverters (MLIs) and power converter circuits comprising at least one VLMM and a MLI are described herein. The VLMM is configured to receive a first output voltage from the MLI having a first number of voltage levels and to generate a second output voltage having a second number of voltage levels. If the first number of voltage levels is M, and the VLMM is N-fold voltage level multiplier, then second number of voltage levels is M×N+1. Switching pattern generators for use with the VLMM and modulation methods for controlling switching elements of the VLMM are also described herein.