Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.

An example of a device for generating a broadband frequency signal comprises a first controlled oscillator, a second controlled oscillator, a phase-locked loop for feeding back an output signal of a controlled oscillator to the corresponding controlled oscillator, and a mixer. The mixer is configured to generate the broadband frequency signal by mixing an output signal of the first controlled oscillator and an output signal of the second controlled oscillator. The device may, for example, be realized by means of a single phase-locked loop. A further example relates to a device for generating a frequency signal with a controlled oscillator and a phase-locked loop with a further controlled oscillator and a mixer in the feedback path of the phase-locked loop. Examples further relate to a high-frequency device for emitting a high-frequency signal and a method for generating a broadband frequency signal.

Networks of superharmonic injection-locked (SHIL) electronic oscillators can be used to emulate Ising machines for solving difficult computational problems. The oscillators can be simulated or implemented in hardware (e.g., with LC oscillators) and are coupled to each other with links whose connection strengths are weighted according to the problem being solved. The oscillators' phases may be measured with respect to reference signal(s) from one or more reference oscillators, each of which emits a reference signal but does not receive input from any other oscillator. Sparsely connected networks of SHIL oscillators and reference oscillators can be used as Viterbi decoders that do not suffer from the information bottleneck between logic computational blocks and memory in digital computing systems. Sparsely connected networks of SHIL oscillators and reference oscillators can also be programmed to act as Boolean logic gates that operate in both forward and backward directions, enabling multipliers that can factor numbers.

Inductor-capacitor oscillators and common mode resonators are provided. The inductor-capacitor oscillator includes a first transistor, a second transistor, an inductor, a first capacitor, a second capacitor, a first winding, and a second winding. The first transistor has a first terminal, a second terminal, and a third terminal. The second transistor has a fourth terminal, a fifth terminal and a sixth terminal. The first, second and third terminals are electrically connected to the fifth, fourth and sixth terminals, respectively. The first capacitor and the inductor are coupled between the first terminal and the fourth terminal. The second capacitor is coupled between the third terminal and a reference voltage. The first winding is coupled between the third terminal and the reference voltage. The second winding is coupled between the third terminal and the reference voltage. The first winding and the second winding are symmetric to each other.

An IQ signal source (100) includes: a Q-VCO (3) having a first VCO (1) and a second VCO (2), the IQ signal source (100) outputting an I signal and a Q signal by electrically coupling the first VCO (1) and the second VCO (2) with each other; a first PLL (10) for comparing a frequency of the I signal or the Q signal with a frequency of a reference signal input from the outside of the IQ signal source (100) and outputting a voltage depending on a result of the comparison; and a second PLL (9) for detecting an IQ phase difference and outputting a voltage depending on the IQ phase difference. The IQ phase difference converges to 90 degrees in dependence on the output voltage of the first PLL (10) and the output voltage of the second PLL (9).

A variable reactance apparatus, tunable oscillator and method for changing a gain associated with an input signal of a tunable oscillator are disclosed. An embodiment of the variable reactance apparatus comprises includes a plurality of unit variable reactance structures comprising including respective control input nodes, and a control circuit configured to connect each of the control input nodes to a respective signal from among a plurality of signals comprising including a first tuning signal and a second tuning signal. An embodiment of a tunable oscillator comprises includes a resonance circuit, a negative impedance structure and a variable reactance apparatus configured for tuning of the oscillator. An embodiment of a method comprises includes altering connections of first and second tuning signals to control input nodes of respective first and second sets of unit variable reactance structures while holding constant a sum of the number of unit variable reactance structures in the first and second sets.

A quadrature voltage-controlled oscillator circuit with phase shift includes two voltage-controlled oscillators with the same structure, wherein the two voltage-controlled oscillators are connected to each other through input and output ports, and the two voltage-controlled oscillators respectively include a cross-coupled oscillating circuit, an injection locking circuit, a resonant circuit and a voltage-controlled current source circuit which are electrically connected to each other; and signals are injected through the injection locking circuit and coupled with the oscillating circuit, so as to output a quadrature signal. An oscillator is enabled to operate stably in one mode by means of a simple circuit structure, and a good phase shift can be provided for the resonant circuit in a lower frequency band; and meanwhile, a tuning range of the oscillator is improved without increasing phase noise.

In semiconductor integrated circuitry having metal layers and via layers sandwiched between adjacent said metal layers, a capacitor is formed from metal structures implemented in first to third metal layers. The metal structures comprise strips having widths parallel to the layers. The strips of the first layer form a first comb having a base strip and a plurality of finger strips extending from the base strip, the widths of the strips being in a lower range of widths. The strips of the second layer form a second comb having a base strip and a plurality of finger strips extending from the base strip, the widths of the finger strips being in the lower range of widths. The width of each base strip formed in the second layer is in an intermediate range of widths; and the strips formed in the third layer have widths in a higher range of widths.

An IQ signal source (100) includes: a Q-VCO (3) having a first VCO (1) and a second VCO (2), the IQ signal source (100) outputting an I signal and a Q signal by electrically coupling the first VCO (1) and the second VCO (2) with each other; a first PLL (10) for comparing a frequency of the I signal or the Q signal with a frequency of a reference signal input from the outside of the IQ signal source (100) and outputting a voltage depending on a result of the comparison; and a second PLL (9) for detecting an IQ phase difference and outputting a voltage depending on the IQ phase difference. The IQ phase difference converges to 90 degrees in dependence on the output voltage of the first PLL (10) and the output voltage of the second PLL (9).

A system for correcting a duty cycle comprises a digital quadrature generator circuit, a frequency doubler circuit, a first duty cycle correction circuit coupled between the digital quadrature generator circuit and the frequency doubler circuit, and a second duty cycle correction circuit coupled between the digital quadrature generator circuit and the frequency doubler circuit. The first duty cycle correction circuit comprises a first stacked duty cycle correction circuit and the second duty cycle correction circuit comprises a second stacked duty cycle correction circuit.