An amplifier circuit has an output stage, a first current source, a second current source, a third current source, a fourth current source, and a voltage clamping voltage. The output stage has a first P-type transistor and a first N-type transistor. The voltage clamping circuit receives a first bias voltage and a second bias voltage, and has a first end and a second end. When a second input current is positive current and the input current is a negative current or a zero current, the first end provides a first clamping voltage greater than the first bias voltage to a gate of the first P-type transistor. When the first input current is positive and the second input current is a negative current or zero current, the second end provides a second clamping voltage lower than the second bias voltage to a gate of the first N-type transistor.

An output buffer for a source driver of a panel includes an output stage, configured to output an output voltage; an operational transconductance amplifier (OTA), configured to control the output stage to charge or discharge a capacitor of a pixel of the panel; and a detector, coupled between the OTA and the output stage, configured to output an enabling signal to turn on/off the output buffer after the output buffer finishes charging or discharging the capacitor of the pixel of the panel, wherein the enabling signal is determined according to a current value of the output stage.

An apparatus and method for analog to digital conversion of analog input signals are disclosed herein. In some embodiments, an analog-to-digital (ADC) may comprise: a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit and a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit, wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region.

An amplifier circuit has: a first amplifier circuit, including a chopper circuit amplifying a first differential signal input between first and second input terminals to output a second differential signal; and a second amplifier circuit amplifying the second differential signal to output a single-ended signal. The second amplifier circuit includes: a first circuit including first and second transistors, the first circuit being connected to the first amplifier circuit so that the second differential signal input into gates of these transistors, the first circuit converting the second differential signal to a current flowing into a first node connected to the first transistor and a current flowing into a second node connected to the second transistor; and a second circuit negatively feeding back a voltage at the second node so that the difference in voltage between these nodes is reduced. The second amplifier circuit outputs the single-ended signal from the first node.

An amplifier includes an input circuit that amplifies a difference between a first input voltage and a second input voltage to generate a first current and a second current. A positive feedback circuit amplifies a difference between the first current and the second current to generate a third current and a fourth current and outputs a difference between the third current and the fourth current through an output node. A temperature compensation circuit adjusts an amplification factor of the positive feedback circuit in response to a change of temperature.

An apparatus and method for analog to digital conversion of analog input signals are disclosed herein. In some embodiments, an analog-to-digital (ADC) may comprise: a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit and a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit, wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region.

A circuit including an amplifier having an input and an output. The circuit also includes a current-to-voltage amplifier having an input. The circuit further includes a current mirror coupled between the output of the amplifier and the input of the current-to-voltage amplifier. The current mirror is configured to chop current flowing through the first current mirror.

A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.

A circuit including an amplifier having an input and an output. The circuit also includes a current-to-voltage amplifier having an input. The circuit further includes a current mirror coupled between the output of the amplifier and the input of the current-to-voltage amplifier. The current mirror is configured to chop current flowing through the first current mirror.

A circuit including an amplifier having an input and an output. The circuit also includes a current-to-voltage amplifier having an input. The circuit further includes a current mirror coupled between the output of the amplifier and the input of the current-to-voltage amplifier. The current mirror is configured to chop current flowing through the first current mirror.